Vertical transport field-effect transistor including dual layer top spacer

Patent metadata

Field	Value
Publication number	US-10559672-B2
Application number	US-201916252670-A
Country	US
Kind code	B2
Filing date	Jan 20, 2019
Priority date	Dec 4, 2017
Publication date	Feb 11, 2020
Grant date	Feb 11, 2020

Abstract

A vertical transport field-effect transistor includes a top source/drain region separated from an underlying gate stack by a multi-layer top spacer that includes an oxygen barrier layer beneath a top dielectric layer. Techniques for fabricating the transistor include depositing the oxygen barrier layer over the gate stack prior to depositing the top dielectric layer. The oxygen barrier layer blocks oxygen diffusion during deposition of the top dielectric layer, thereby avoiding damage to underlying interfacial and gate dielectric layers.

First claim

What is claimed is:

1. A method of fabricating vertical transport transistor structures, comprising:
providing a monolithic structure including:
a semiconductor substrate,
first and second parallel semiconductor fins, each of the first and second parallel semiconductor fins including a bottom region adjoining the semiconductor substrate, a top region and a channel region between the bottom region and the top region, and
a dielectric cap on the top region of each of the first and second semiconductor fins;

epitaxially growing a bottom source/drain region adjoining the bottom regions of the first and second semiconductor fins directly on a top surface of the semiconductor substrate;
depositing a bottom electrically insulating spacer over the bottom source/drain region;
depositing a gate dielectric layer over the bottom electrically insulating spacer and the first and second parallel semiconductor fins;
depositing a work function metal layer directly on the gate dielectric layer;
recessing the gate dielectric layer and the work function metal layer, thereby exposing the top regions of the first and second parallel semiconductor fins and top edge portions of the gate dielectric layer;
depositing an oxidation barrier layer over the work function metal layer, the top regions of the first and second parallel semiconductor fins, the top edge portions of the gate dielectric layer, and the dielectric caps;
depositing a top dielectric layer over the oxidation barrier layer;
recessing the oxidation barrier layer and the top dielectric layer, thereby exposing sidewalls of the top regions of the first and second parallel semiconductor fins;
removing the dielectric caps from the first and second parallel semiconductor fins; and
epitaxially growing first and second top source/drain regions directly on the sidewalls of the top regions of the first and second parallel semiconductor fins such that a portion of the oxidation barrier layer and a portion of the top dielectric layer comprise first and second top spacers positioned respectively between the first and second top source/drain regions and the gate electrode layer.

2. The method of claim 1 , wherein the oxygen barrier layer includes aluminum oxide.

3. The method of claim 2 , wherein the first and second parallel semiconductor fins comprise silicon.

4. The method of claim 3 , wherein the top dielectric layer comprises silicon nitride.

5. The method of claim 4 , further including:
depositing contact metal on the first and second top source/drain regions.

Assignees

• IBM

Inventors

• Jagannathan Hemanth
• Lee Choonghyun
• Reznicek Alexander
• Waskiewicz Christopher

Classifications

• H10D64/01354

  passivation or protection of the electrode, e.g. using re-oxidation · CPC title

• H01L29/66666

  Electricity · mapped topic

• H01L29/0653

  Electricity · mapped topic

• H01L29/6653

  Electricity · mapped topic

• H01L29/7827

  Electricity · mapped topic