Bottom source/drain silicidation for vertical field-effect transistor (FET)

Patent metadata

Field	Value
Publication number	US-9805935-B2
Application number	US-201514985943-A
Country	US
Kind code	B2
Filing date	Dec 31, 2015
Priority date	Dec 31, 2015
Publication date	Oct 31, 2017
Grant date	Oct 31, 2017

Abstract

A method for manufacturing a semiconductor device includes forming a first active region on a semiconductor substrate, forming a semiconductor layer on the first active region, patterning the semiconductor layer into a plurality of fins extending from the first active region vertically with respect to the semiconductor substrate, wherein the first active region is located at bottom ends of the plurality of fins, forming a silicide layer on exposed portions of the first active region, forming an electrically conductive contact on the silicide region, forming a second active region on top ends of each of the plurality of fins, and forming a gate structure between the plurality of fins, wherein the gate structure is positioned over the first active region and under the second active region.

First claim

We claim:

1. A method for manufacturing a semiconductor device, comprising:
forming a source/drain region on a semiconductor substrate;
forming a semiconductor layer on the source/drain region;
patterning the semiconductor layer into a plurality of fins extending from the source/drain region vertically with respect to the semiconductor substrate, wherein the source/drain region is located under bottom ends of the plurality of fins;
forming a silicide layer on exposed portions of the source/drain region;
forming an electrically conductive contact on the silicide layer; and
forming a spacer layer on the silicide layer, wherein the electrically conductive contact extends through an opening in the spacer layer to contact the silicide layer;
wherein the semiconductor device comprises a vertical field-effect transistor (FET) device configured to carry current through the plurality of fins in a direction perpendicular to a top surface of the semiconductor substrate on which the source/drain region is formed and from which the plurality fins vertically extend.

2. The method according to claim 1 , wherein the silicide layer wraps around an edge of the source/drain region.

3. The method according to claim 1 , further comprising forming a protective layer on the plurality of fins prior to forming the silicide layer on the exposed portions of the source/drain region.

4. The method according to claim 1 , further comprising:
removing a portion of the source/drain region and a portion of the substrate under the source/drain region to form a trench; and
filling the trench with a dielectric material to form an isolation region.

5. The method according to claim 4 , further comprising recessing the isolation region to expose an edge of the source/drain region prior to forming the silicide layer on the exposed portions of the source/drain region.

6. The method according to claim 1 , further comprising:
forming a gate structure on the spacer layer and on the plurality of fins; and
patterning the gate structure to remove a portion of the gate structure to expose a portion of the spacer layer where the opening through which the electrically conductive contact extends will be formed.

7. The method according to claim 6 , further comprising recessing the gate structure between the plurality of fins.

8. The method according to claim 7 , further comprising forming another spacer layer on the recessed gate structure.

9. The method according to claim 1 , wherein the spacer layer comprises at least one of an oxide, silicon nitride (SiN), siliconborocarbonitride (SiBCN), and silicon oxycarbonitride (SiOCN).

10. The method according to claim 1 , further comprising forming another source/drain region on top ends of each of the plurality of fins.

11. The method according to claim 10 , forming a gate structure over the silicide layer and between the plurality of fins, wherein the gate structure is positioned under the other source/drain region.

12. A method for manufacturing a semiconductor device, comprising:
forming a first active region on a semiconductor substrate;
forming a semiconductor layer on the first active region;
patterning the semiconductor layer into a plurality of fins extending from the first active region vertically with respect to the semiconductor substrate, wherein the first active region is located under bottom ends of the plurality of fins;
forming a silicide layer on exposed portions of the first active region;
forming an electrically conductive contact on the silicide layer;
forming a second active region on top ends of each of the plurality of fins;
forming a gate structure between the plurality of fins, wherein the gate structure is positioned over the first active region and under the second active region; and
forming a spacer layer on the silicide layer, wherein the electrically conductive contact extends through an opening in the spacer layer to contact the silicide layer;
wherein the semiconductor device comprises a vertical field-effect transistor (FET) device configured to carry current through the plurality of fins in a direction perpendicular to a top surface of the semiconductor substrate on which the first active region is formed and from which the plurality fins vertically extend.

13. The method according to claim 12 , wherein the silicide layer wraps around an edge of the first active region.

14. The method according to claim 12 , further comprising forming a protective layer on the plurality of fins prior to forming the silicide layer on the exposed portions of the first active region.

15. The method according to claim 12 , further comprising:
removing a portion of the first active region and a portion of the substrate under the first active region to form a trench; and
filling the trench with a dielectric material to form an isolation region.

16. The method according to claim 15 , further comprising recessing the isolation region to expose an edge of the first active region prior to forming the silicide layer on the exposed portions of the first active region.

17. The method according to claim 12 , wherein the gate structure is formed on the spacer layer, and the method further comprises patterning the gate structure to remove a portion of the gate structure to expose a portion of the spacer layer where the opening through which the electrically conductive contact extends will be formed.

18. The method according to claim 17 , further comprising recessing the gate structure between the plurality of fins.

Assignees

• IBM

Inventors

• Anderson Brent A
• Bu Huiming
• Hook Terence B
• Lie Fee Li
• Wang Junli

Classifications

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10D64/0112 Primary

  using conductive layers comprising silicides · CPC title

• H01L29/0649

  Electricity · mapped topic

• H01L29/41791

  Electricity · mapped topic

• H01L29/66795

  Electricity · mapped topic