Multiple gate length vertical field-effect-transistors

Patent metadata

Field	Value
Publication number	US-9570356-B1
Application number	US-201514961179-A
Country	US
Kind code	B1
Filing date	Dec 7, 2015
Priority date	Dec 7, 2015
Publication date	Feb 14, 2017
Grant date	Feb 14, 2017

Abstract

Various embodiments disclose a method for fabricating a semiconductor structure. In one embodiment, the method includes forming a masking layer over at least a first portion of a source contact layer formed on a substrate. At least a second portion of the source contact layer is recessed below the first portion of the source contact layer. The mask layer is removed and a first spacer layer, a replacement gate on the first spacer layer, a second spacer layer on the replacement gate, and an insulating layer on the second spacer layer are formed. First and second trenches are then formed. A first channel layer is epitaxially grown within the first trench. A second channel layer is epitaxially grown within the second trench. A length of the second channel layer is greater than a length of the first channel layer.

First claim

What is claimed is:

1. A method for fabricating a semiconductor structure comprising a plurality of vertical transistors each having different gate lengths, the method comprising:
form a masking layer over at least a first portion of a source contact layer formed on a substrate;
recessing at least a second portion of the source contact layer below the first portion of the source contact layer;
removing the masking layer and forming a first spacer layer on the first and second portions of the source contact layer, a replacement gate on the first spacer layer, a second spacer layer on the replacement gate, and an insulating layer on the second spacer layer;
forming a first trench extending from a top surface of the insulating layer down to a top surface of the first portion of the source contact layer;
forming a second trench extending from the top surface of the insulating layer down to a top surface of the second portion of the source contact layer;
epitaxially growing a first channel layer within the first trench from the first portion of the source contact layer; and
epitaxially growing a second channel layer within the second trench from the second portion of the source contact layer, wherein a length of the second channel layer is greater than a length of the first channel layer.

2. The method of claim 1 , further comprising:
forming a counter-doped layer between the substrate and the source contact layer.

3. The method of claim 1 , further comprising:
prior to epitaxially growing the first channel layer, forming a protective layer on exposed portions of the replacement gate within the first trench; and
prior to epitaxially growing the second channel layer, forming a protective layer on exposed portions of the replacement gate within the second trench.

4. The method of claim 1 , further comprising:
recessing the first and second channel layers, the recessing leaving a first portion of the first and second channel layers above the second spacer layer;
after the recessing, forming a first mask above and in contact with the first channel layer and forming a second mask above and in contact with second channel layer;
after forming the first and second masks, removing the insulating layer exposing the first portion of the first and second channel layers; and
performing a lateral etch of the first portion of the first and second channel layers, the lateral etch narrowing the first portion of the first and second channel layers and a second portion of the first and second channel layers below a top surface of the second spacer layer.

5. The method of claim 4 , further comprising:
forming a first drain region and second drain region on the first and second portions of the first and second channel layers, respectively.

6. The method of claim 5 , further comprising:
forming a third spacer layer on and in contact with sidewalls of the first mask and sidewalls of the first drain region, the third spacer layer also being formed on and in contact with a top surface of the second spacer layer in a first region corresponding to the first portion of the structure; and
forming a fourth spacer layer on sidewalls of the second mask and sidewalls of the second drain region, the fourth spacer layer also being formed on and in contact with a top surface of the second spacer layer in a second region corresponding to the second portion of the structure.

7. The method of claim 6 , further comprising:
removing portions of the structure not underlying the third and fourth spacer layers down to the first spacer layer.

8. The method of claim 7 , further comprising:
removing a portion of the replacement gate under the third spacer layer and a portion of the replacement gate under the fourth spacer layer, the removing exposing sidewalls of the first channel layer and the second channel layer.

9. The method of claim 8 , further comprising:
forming a first metal gate structure on and in contact with the exposed sidewalls of the first channel layer, a portion of the first spacer layer under the third spacer layer, and a portion of the second spacer layer under the third spacer layer; and
forming a second metal gate structure on and in contact with the exposed sidewalls of the second channel layer, a portion of the first spacer layer under the fourth spacer layer, and a portion of the second spacer layer under the fourth spacer layer.

10. The method of claim 9 , wherein forming each of the first and second metal gate structure comprises:
forming a first dielectric layer on and in contact with the exposed sidewalls of the first channel layer, the portion of the first spacer layer under the third spacer layer, and the portion of the second spacer layer under the third spacer layer; and
forming a second dielectric layer on and in contact with the exposed sidewalls of the second channel layer, the portion of the first spacer layer under the fourth spacer layer, and the portion of the second spacer layer under the fourth spacer layer.

11. The method of claim 10 , wherein forming each of the first and second metal gate structure further comprises:
forming a first metal layer in contact with and conforming to the first dielectric layer; and
forming a second metal layer in contact with and conforming to the second dielectric layer.

12. The method of claim 9 , further comprising:
forming recessed metal gate fill layers on each side of the first and second metal gate structures;
depositing a dielectric layer over the first and second regions of the structure;
forming a first contact trench through the dielectric layer exposing at least a top surface of the recessed metal gate fill layer on at least a first side of the first metal gate structure;
forming a second contact trench through the dielectric layer exposing at least a top surface of the recessed metal gate fill layer on at least a first side of the second metal gate structure;
forming a third contact trench exposing a top surface of the first drain region and a top surface of the first portion of the first channel layer;
forming a fourth contact trench exposing a top surface of the second drain region and a top surface of the first portion of the second channel layer; and
forming a contact in each of the first, second, third, and fourth contact trenches.

Assignees

• IBM

Inventors

• Balakrishnan Karthik
• Cheng Kangguo
• Hashemi Pouya
• Reznicek Alexander

Classifications

• H10P50/692

  characterised by their composition, e.g. multilayer masks or materials · CPC title

• H10P14/40

  of conductive or resistive materials · CPC title

• H01L21/283

  Electricity · mapped topic

• H01L29/66666

  Electricity · mapped topic

• H01L27/088

  Electricity · mapped topic