Air-gap top spacer and self-aligned metal gate for vertical fets

Patent metadata

Field	Value
Publication number	US-9735246-B1
Application number	US-201615152144-A
Country	US
Kind code	B1
Filing date	May 11, 2016
Priority date	May 11, 2016
Publication date	Aug 15, 2017
Grant date	Aug 15, 2017

Abstract

Transistors and method of forming he same include forming a fin on a bottom source/drain region having a channel region and a sacrificial region on the channel region. A gate stack is formed on sidewalls of the channel region. A gate conductor is formed in contact with the gate stack that has a top surface that meets a middle point of sidewalls of the sacrificial region. The sacrificial region is trimmed to create gaps above the gate stack. A top spacer is formed on the gate conductor having airgaps above the gate stack.

First claim

What is claimed is:

1. A method for forming a transistor, comprising:
forming a fin on a bottom source/drain region comprising a channel region and a sacrificial region on the channel region;
forming a gate stack on sidewalls of the channel region;
forming a gate conductor in contact with the gate stack that has a top surface that meets a middle point of sidewalls of the sacrificial region;
trimming the sacrificial region to create gaps above the gate stack; and
forming a top spacer on the gate conductor having airgaps above the gate stack.

2. The method of claim 1 , further comprising forming a top source/drain region directly on a top surface of the channel region after forming the top spacer.

3. The method of claim 1 , wherein forming the fin comprises etching a stack comprising a first layer of a first semiconductor material and a second layer of a second semiconductor material to form a channel layer from the first semiconductor material and to form the sacrificial region from the second semiconductor material.

4. The method of claim 3 , wherein the first semiconductor material is silicon and the second semiconductor material is silicon germanium.

5. The method of claim 3 , further comprising forming a bottom spacer directly on the bottom source/drain region around the fin.

6. The method of claim 3 , wherein forming the fin further comprises laterally etching the channel layer to form the channel region, such that the sacrificial region overhangs sidewalls of the channel region.

7. The method of claim 1 , wherein trimming the sacrificial region comprises trimming the sacrificial region to a same width as the channel region.

8. The method of claim 1 , wherein forming the top spacer comprises a non-conformal dielectric deposition process.

9. The method of claim 1 , wherein forming the top spacer comprises forming a first dielectric layer and forming a second dielectric layer having a lower dielectric constant than the first dielectric layer.

10. A method for forming a transistor, comprising:
forming a fin on a bottom source/drain region comprising a channel region and a sacrificial region on the channel region by:
etching a stack comprising a first layer of a silicon and a second layer of silicon germanium to form a channel layer from the first layer and to form the sacrificial region from the second layer; and
laterally trimming the channel layer to form the channel region, such that the sacrificial region overhangs sidewalls of the channel region;
forming a bottom spacer directly on the bottom source/drain region and around the fin;
forming a gate stack on sidewalls of the channel region;
forming a gate conductor in contact with the gate stack that has a top surface that meets a middle point of sidewalls of the sacrificial region;
trimming the sacrificial region to create gaps above the gate stack;
forming a top spacer on the gate conductor having airgaps above the gate stack; and
forming a top source/drain region directly on a top surface of the channel region after forming the top spacer, the top spacer comprising a first dielectric layer and a second directly layer directly on the first dielectric layer, the second dielectric layer having a lower dielectric constant than the first dielectric layer.

11. The method of claim 10 , wherein trimming the sacrificial region comprises trimming the sacrificial region to a same width as the channel region.

12. The method of claim 10 , wherein forming the top spacer comprises a non-conformal dielectric deposition process.

Assignees

• IBM

Inventors

• Basker Veeraraghavan S
• Cheng Kangguo
• Standaert Theodorus E
• Wang Junli

Classifications

• H10P95/064

  the removal being chemical etching · CPC title

• H10P95/04

  Planarisation of conductive or resistive materials · CPC title

• H10P50/692

  characterised by their composition, e.g. multilayer masks or materials · CPC title

• H10P50/642

  Chemical etching · CPC title

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title