Vertical transistor with air-gap spacer

Patent metadata

Field	Value
Publication number	US-9368572-B1
Application number	US-201514948257-A
Country	US
Kind code	B1
Filing date	Nov 21, 2015
Priority date	Nov 21, 2015
Publication date	Jun 14, 2016
Grant date	Jun 14, 2016

Abstract

A vertical transistor has a first air-gap spacer between the gate and the bottom source/drain, and a second air-gap spacer between the gate and the contact to the bottom source/drain. A dielectric layer disposed between the gate and the contact to the top source/drain decreases parasitic capacitance and inhibits electrical shorting.

First claim

What is claimed as new is:

1. A method of making a vertical transistor, comprising:
forming a fin or a vertical nanowire over a semiconductor substrate;
forming a gate electrode over sidewalls of the fin or vertical nanowire;
forming a sacrificial spacer over the gate electrode;
forming a bottom source/drain contact adjacent to the sacrificial spacer;
removing the sacrificial spacer to create a cavity between the gate electrode and the bottom source/drain contact;
non-conformally depositing a dielectric material into the cavity and between the gate electrode and the substrate, wherein the dielectric material comprises a vertical air-gap and the dielectric material between the gate electrode and the substrate comprises a horizontal air-gap.

2. The method of claim 1 , wherein a distance between the gate electrode and the bottom source/drain contact is between 4 nm and 20 nm.

3. The method of claim 1 , wherein the vertical air-gap height is from 15 nm to 50 nm and the vertical air-gap width is from 4 nm to 20 nm.

4. The method of claim 1 , further comprising depositing a conformal dielectric layer directly over each of the gate electrode and the bottom source/drain contact prior to non-conformally depositing the dielectric material.

5. The method of claim 1 , wherein the horizontal air-gap height is from 4 nm to 20 nm and the horizontal air-gap width is from 30 nm to 50 nm.

6. The method of claim 1 , wherein the horizontal air-gap and the vertical air-gap are interconnected.

7. The method of claim 1 , wherein the dielectric spacer is disposed between the gate electrode and a top source/drain contact.

Assignees

• IBM

Inventors

• Cheng Kangguo
• Ning Tak H

Classifications

• H10W20/072

  of dielectric parts comprising air gaps · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/46

  comprising air gaps · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10W10/021

  of air gaps · CPC title