Vertical transport field-effect transistor including air-gap top spacer

Patent metadata

Field	Value
Publication number	US-10559671-B2
Application number	US-201916404704-A
Country	US
Kind code	B2
Filing date	May 6, 2019
Priority date	Dec 4, 2017
Publication date	Feb 11, 2020
Grant date	Feb 11, 2020

Abstract

A vertical transport field-effect transistor includes a top source/drain region separated from an underlying gate stack by a top spacer including open gaps to reduce capacitance therebetween. Techniques for fabricating the transistor include using a sacrificial spacer that is selectively removed prior to growth of the top source/drain region. The top source/drain region may be confined by opposing dielectric layers.

First claim

What is claimed is:

1. A vertical transport field-effect transistor structure, comprising:
a substrate;
a semiconductor fin extending vertically with respect to the substrate, the semiconductor fin including a top region, a bottom region, and a channel region between the top region and the bottom region;
a bottom source/drain region adjoining the bottom region of the semiconductor fin;
a gate dielectric layer adjoining the channel region of the semiconductor fin;
an electrically conductive gate electrode layer adjoining the gate dielectric layer;
a bottom dielectric spacer between the bottom source/drain region and the gate electrode layer;
first and second vertically extending dielectric layers;
a cavity bounded by the first and second vertically extending dielectric layers, the top region of the semiconductor fin extending within the cavity;
first and second divots extending downwardly from the cavity and located between the top region of the semiconductor fin and the first and second vertically extending dielectric layers;
a faceted, epitaxial top source/drain region on the top region of the semiconductor fin and within the cavity;
a dielectric liner extending over the gate dielectric layer and the gate electrode layer; and
a top spacer comprising first and second open gaps between the faceted, epitaxial top source/drain region and the dielectric liner.

2. The vertical transport field-effect transistor structure of claim 1 , further wherein the faceted, epitaxial top source/drain region contacts the first and second vertically extending dielectric layers.

3. The vertical transport field-effect transistor structure of claim 2 , wherein the fin is integral with the substrate and the bottom source/drain layer is epitaxial with respect to the substrate.

4. The vertical transport field-effect transistor structure of claim 3 , wherein the dielectric liner includes U-shaped portions including vertical segments adjoining the top region of the semiconductor fin.

5. The vertical transport field-effect transistor structure of claim 3 , wherein the substrate comprises silicon.

6. The vertical transport field-effect transistor structure of claim 5 , further including a metal contact within the cavity and extending above the top source/drain region.

7. The vertical transport field-effect transistor structure of claim 5 , wherein the top region of the fin and each of the first and second vertically extending dielectric layers are separated by a distance of about ten nanometers.

Assignees

• IBM

Inventors

• Jagannathan Hemanth
• Lee Choonghyun
• Reznicek Alexander
• Waskiewicz Christopher

Classifications

• H01L29/66666

  Electricity · mapped topic

• H01L29/66553 Primary

  Electricity · mapped topic

• H01L29/0653

  Electricity · mapped topic

• H01L29/6653

  Electricity · mapped topic

• H01L29/7827

  Electricity · mapped topic