Three-dimensional semiconductor devices including vertical structures

Patent metadata

Field	Value
Publication number	US-10553598-B2
Application number	US-201816012046-A
Country	US
Kind code	B2
Filing date	Jun 19, 2018
Priority date	Nov 20, 2017
Publication date	Feb 4, 2020
Grant date	Feb 4, 2020

Abstract

A three-dimensional semiconductor device is provided including a gate electrode disposed on a substrate and having a pad region, a cell vertical structure passing through the gate electrode, a dummy vertical structure passing through the pad region, and a gate contact plug disposed on the pad region. The cell vertical structure includes a cell pad layer disposed on a level higher than that of the gate electrode and a cell channel layer opposing the gate electrode, the dummy vertical structure includes a buffer region formed of a material different from that of the cell pad layer and a dummy channel layer formed of a material the same as that of the cell channel layer, and at least a portion of the buffer region is located on the same plane as at least a portion of the cell pad layer.

First claim

What is claimed is:

1. A three-dimensional semiconductor device, comprising:
a gate electrode on a substrate and having a pad region;
a cell vertical structure passing through the gate electrode;
a dummy vertical structure passing through the pad region; and
a gate contact plug on the pad region,
wherein the cell vertical structure includes a cell pad layer on a level higher than that of the gate electrode and a cell channel layer opposing the gate electrode;
wherein the dummy vertical structure includes a buffer region including a material different from a material of the cell pad layer and a dummy channel layer including a same material as a material of the cell channel layer; and
wherein at least a portion of the buffer region is on a same plane as at least a portion of the cell pad layer.

2. The three-dimensional semiconductor device of claim 1 , wherein the buffer region includes a lower portion and an upper portion on the lower portion.

3. The three-dimensional semiconductor device of claim 2 , wherein the upper portion of the buffer region is located on a same plane as the cell pad layer.

4. The three-dimensional semiconductor device of Claim
wherein the cell vertical structure further includes a cell core pattern;
wherein the dummy vertical structure further includes a dummy core pattern including a same material as a material of the cell core pattern and having a greater width than that of the cell core pattern;
wherein the cell pad layer is on the cell core pattern;
wherein the cell channel layer is on a side surface of the cell core pattern;
wherein the upper portion of the buffer region is on the dummy core pattern; and
wherein the lower portion of the buffer region and the dummy channel layer are on a side surface of the dummy core pattern.

5. The three-dimensional semiconductor device of claim 1 , wherein a boundary between the buffer region and the dummy channel layer includes a first boundary portion and a second boundary portion, located on different levels.

6. The three-dimensional semiconductor device of claim 1 , wherein the gate contact plug is in contact with the buffer region of the dummy vertical structure.

7. The three-dimensional semiconductor device of claim 1 , further comprising:
a bit line contact plug on the cell pad layer and electrically connected to the cell pad layer;
a bit line electrically connected to the bit line contact plug; and
gate dielectric layers between the cell vertical structure and the gate electrode,
wherein one among the gate dielectric layers is a data storage layer storing data.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Jung Young Jin

Classifications

• G11C7/18

  Bit line organisation; Bit line lay-out · CPC title

• G11C8/10

  Decoders · CPC title

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title

• H01L27/11556 Primary

  Electricity · mapped topic

• H01L29/42328

  Electricity · mapped topic