Stack of horizontally extending and vertically overlapping features, methods of forming circuitry components, and methods of forming an array of memory cells

Patent metadata

Field	Value
Publication number	US-9564471-B2
Application number	US-201615095208-A
Country	US
Kind code	B2
Filing date	Apr 11, 2016
Priority date	Apr 12, 2011
Publication date	Feb 7, 2017
Grant date	Feb 7, 2017

Abstract

A method of forming circuitry components includes forming a stack of horizontally extending and vertically overlapping features. The stack has a primary portion and an end portion. At least some of the features extend farther in the horizontal direction in the end portion moving deeper into the stack in the end portion. Operative structures are formed vertically through the features in the primary portion and dummy structures are formed vertically through the features in the end portion. Horizontally elongated openings are formed through the features to form horizontally elongated and vertically overlapping lines from material of the features. The lines individually extend from the primary portion into the end portion, and individually laterally about sides of vertically extending portions of both the operative structures and the dummy structures. Sacrificial material that is elevationally between the lines is at least partially removed in the primary and end portions laterally between the horizontally elongated openings. Other aspects and implementations are disclosed.

First claim

The invention claimed is:

1. A stack of horizontally extending and vertically overlapping features, the stack comprising:
a primary portion and an end portion, at least some of the features extending farther in the horizontal direction in the end portion moving deeper into the stack in the end portion;
operative structures extending vertically through the features in the primary portion; and
dummy structures extending vertically through the features in the end portion.

2. The stack of claim 1 further comprising contacts in the end portion.

3. The stack of claim 1 wherein the features comprise horizontally extending conductive lines.

4. The stack of claim 1 wherein the operative and dummy structures comprise the same material.

5. The stack of claim 4 wherein the operative and dummy structures comprise a plurality of the same materials.

6. The stack of claim 5 wherein the same materials are arranged in the same lateral order relative one another in the operative and dummy structures.

7. The stack of claim 4 wherein the operative and dummy structures consist essentially of the same material.

8. The stack of claim 1 wherein the features comprise plates.

9. The stack of claim 1 wherein the operative and dummy structures comprise programmable material.

10. The stack of claim 1 wherein the operative and dummy structures comprise semiconductive material.

11. The stack of claim 10 wherein the semiconductive material of the operative structures comprises interconnected channels of a plurality of vertically oriented transistors.

12. The stack of claim 11 wherein the interconnected channels are of vertically oriented charge storage transistors.

13. The stack of claim 11 wherein the operative and dummy structures comprise conductive material.

14. The stack of claim 1 wherein the operative and dummy structures comprise hollow cylinders.

15. The stack of claim 1 wherein the operative and dummy structures comprise laterally solid pillars.

16. The stack of claim 1 wherein the operative structures comprises portions of memory cells.

17. The stack of claim 16 wherein the memory cells comprise a portion of NAND architecture, the operative structures comprising interconnected channel regions of a NAND string.

18. The stack of claim 16 wherein the memory cells comprise cross-point memory cells.

Assignees

• Micron Technology Inc

Inventors

• Tang Sanh D
• Lindsay Roger W
• Parat Krishna K

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H10W72/00 Primary

  Interconnections or connectors in packages · CPC title

• G11C2213/11

  Metal ion trapping, i.e. using memory material including cavities, pores or spaces in form of tunnels or channels wherein metal ions can be trapped but do not react and form an electro-deposit creating filaments or dendrites · CPC title

• G11C2213/32

  Material having simple binary metal oxide structure · CPC title

• G11C13/0007

  comprising metal oxide memory material, e.g. perovskites · CPC title