Three-dimensional semiconductor device with vertical and horizontal channels in stack structure having electrodes vertically stacked on the substrate

Patent metadata

Field	Value
Publication number	US-9685452-B2
Application number	US-201615245218-A
Country	US
Kind code	B2
Filing date	Aug 24, 2016
Priority date	Sep 18, 2015
Publication date	Jun 20, 2017
Grant date	Jun 20, 2017

Abstract

A three-dimensional (3D) semiconductor device includes a stack structure including electrodes vertically stacked on a substrate, a channel structure coupled to the electrodes to constitute a plurality of memory cells three-dimensionally arranged on the substrate, the channel structure including first vertical channels and second vertical channels penetrating the stack structure and a first horizontal channel disposed under the stack structure to laterally connect the first vertical channels and the second vertical channels to each other, a second horizontal channel having a first conductivity type and connected to a sidewall of the first horizontal channel of the channel structure, and conductive plugs having a second conductivity type and disposed on top ends of the second vertical channels.

First claim

What is claimed is:

1. A three-dimensional (3D) semiconductor device comprising:
a stack structure comprising electrodes that are vertically stacked on a substrate;
a channel structure coupled to the electrodes to constitute a plurality of memory cells that are three-dimensionally arranged on the substrate, the channel structure comprising:
first vertical channels and second vertical channels that penetrate the stack structure; and
a first horizontal channel that is under the stack structure and that laterally connects the first vertical channels and the second vertical channels to each other;

a second horizontal channel that is connected to a sidewall of the first horizontal channel of the channel structure, the second horizontal channel having a first conductivity type; and
conductive plugs that are on top ends of the second vertical channels, the conductive plugs having a second conductivity type.

2. The 3D semiconductor device of claim 1 , wherein the stack structure, the first horizontal channel, and the second horizontal channel extend in parallel to each other along a direction.

3. The 3D semiconductor device of claim 1 , wherein the first vertical channels are arranged along a first direction and along a second direction that is perpendicular to the first direction, and
wherein the first horizontal channel is connected to the first vertical channels that are arranged along the first direction and the first vertical channels that are arranged along the second direction.

4. The 3D semiconductor device of claim 1 , wherein the first horizontal channel overlaps with the stack structure when viewed from a plan view.

5. The 3D semiconductor device of claim 1 , wherein the first horizontal channel has a rounded sidewall that is in contact with the second horizontal channel.

6. The 3D semiconductor device of claim 1 , wherein the first vertical channels, the second vertical channels, and the first horizontal channel constitute one semiconductor layer that continuously extends without an interface therein.

7. The 3D semiconductor device of claim 1 , wherein the first horizontal channel and the second horizontal channel include a semiconductor material, and
wherein an interface exists between the first horizontal channel and the second horizontal channel.

8. The 3D semiconductor device of claim 1 , wherein the substrate includes a well dopant layer that is doped with dopants of the first conductivity type, and
wherein the second horizontal channel is in direct contact with the well dopant layer.

9. The 3D semiconductor device of claim 1 , further comprising:
a data storage layer that is between the stack structure and the first vertical channels and that is between the stack structure and the second vertical channels; and
a residual data storage pattern that is between the first horizontal channel and the substrate.

10. The 3D semiconductor device of claim 9 , wherein the stack structure further comprises: insulating layers that are between the electrodes, and
wherein the data storage layer extends between a bottom surface of a lowermost insulating layer of the stack structure and the first horizontal channel.

11. The 9D semiconductor device of claim 10 , wherein the second horizontal channel is in contact with a portion of the data storage layer and a portion of the residual data storage pattern.

12. The 3D semiconductor device of claim 1 , wherein bottom surfaces of the conductive plugs are lower than a bottom surface of an uppermost one of the electrodes.

13. The 3D semiconductor device of claim 1 , further comprising:
a conductive line that extends in a first direction on the stack structure and that is connected to the second vertical channels.

14. The 3D semiconductor device of claim 1 , wherein an uppermost one of the electrodes comprises: a first string selection electrode and a second string selection electrode that are laterally spaced apart from each other, and
wherein the second vertical channels are between the first string selection electrode and the second string selection electrode.

15. A three-dimensional (3D) semiconductor device comprising:
a stack structure that extends in a first direction and that includes a plurality of electrodes that are vertically stacked on a substrate;
first vertical channels and second vertical channels that penetrate the stack structure;
a first horizontal channel that extends in the first direction under the stack structure and that connects the first vertical channels and the second vertical channels to each other;
a second horizontal channel that extends in the first direction to contact both sidewalls of the first horizontal channel and has a first conductivity type; and
conductive plugs that are on top ends of the second vertical channels, the conductive plugs having a second conductivity type that different from the first conductivity type.

16. The 3D semiconductor device of claim 15 , wherein the first vertical channels are arranged along the first direction and along a second direction that is perpendicular to the first direction, and
wherein the first horizontal channel is connected to the first vertical channels that are arranged along the first direction and the first vertical channels that are arranged along the second direction.

17. The 3D semiconductor device of claim 15 , wherein the first vertical channels, the second vertical channels, and the first horizontal channel constitute one semiconductor layer that continuously extends without an interface therein, and
wherein an interface exists between the first horizontal channel and the second horizontal channel.

18. The 3D semiconductor device of claim 15 , further comprising:
source plugs that are on top ends of the second vertical channels,
wherein the source plugs have a conductivity type opposite to a conductivity type of the second horizontal channel, and
wherein bottom surfaces of the source plugs are lower than a bottom surface of an uppermost one of the electrodes.

19. The 3D semiconductor device of claim 15 , further comprising:
a data storage layer that is between the stack structure and the first vertical channels and that is between the stack structure and the second vertical channels; and
a residual data storage pattern that is between the first horizontal channel and the substrate,
wherein the stack structure further comprises: insulating layers that are between the electrodes,
wherein the data storage layer extends between a bottom surface of a lowermost insulating layer of the stack structure and the first horizontal channel, and
wherein the second horizontal channel is in contact with a portion of the data storage layer and a portion of the residual data storage pattern.

20. The 3D semiconductor device of claim 15 , further comprising:
a conductive pad that is on a top end of each of the first vertical channels,
wherein the conductive pad has the second conductivity type, and
wherein a bottom surface of the conductive pad is higher than a top surface of an uppermost one of the electrodes.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Changhyun
• Lee Heonkyu
• Kang Shinhwan
• Park Youngwoo

Classifications

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H01L27/1157

  Electricity · mapped topic

• H01L23/535

  Electricity · mapped topic

• H01L27/11582

  Electricity · mapped topic