Field effect transistor with a multilevel gate electrode for integration with a multilevel memory device

Patent metadata

Field	Value
Publication number	US-9620512-B1
Application number	US-201514925224-A
Country	US
Kind code	B1
Filing date	Oct 28, 2015
Priority date	Oct 28, 2015
Publication date	Apr 11, 2017
Grant date	Apr 11, 2017

Abstract

A switching field effect transistor and the memory devices can be formed employing a same set of processing steps. An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory stack structures for memory devices and gate dielectric-channel structures for the field effect transistor can be simultaneously formed in a memory region and in a transistor region, respectively. After replacement of the sacrificial material layers with electrically conductive layers, portions of the electrically conductive layers in a memory region are electrically isolated from one another to provide independently controlled control gate electrodes for the memory devices, while portions of the electrically conductive layers in the transistor region are electrically shorted among one another to provide a single gate electrode for the switching field effect transistor.

First claim

What is claimed is:

1. A device comprising a field effect transistor and a three-dimensional memory device,
wherein the field effect transistor comprises:
a first vertical transistor channel portion extending through a first portion of an alternating stack of electrically conductive layers and insulating layers located over a substrate, wherein at least some of the electrically conductive layers are electrically shorted among one another to provide a gate electrode;
a first gate dielectric laterally surrounding the first vertical transistor channel portion;
a gate electrode contact structure extending through the first portion of the alternating stack and contacting at least some of the electrically conductive layers to electrically short at least some of the electrically conductive layers;
a bottom active region located in, or on, the substrate and laterally spaced from the first vertical transistor channel portion; and
a first top active region overlying the first vertical transistor channel portion,
wherein one of the top and bottom active regions is a source region of the field effect transistor and another of the top and bottom active regions is a drain region of the field effect transistor,

and wherein the three-dimensional memory device comprises:
a second portion of the alternating stack of insulating layers and electrically conductive layers that are electrically isolated from one another and from the electrically conductive layers of the first portion of the alternating stack; and
at least one memory stack structure vertically extending through the second portion of the alternating stack, wherein each of the at least one memory stack structure comprises, from inside to outside, a memory device channel and a memory film.

2. The device of claim 1 , wherein a channel of the field effect transistor comprises the first vertical transistor channel portion and a horizontal channel portion located in or on the substrate, comprising a doped semiconductor material and contacting the bottom active region.

3. The device of claim 2 , wherein:
the channel of the field effect transistor further comprises an epitaxial channel portion comprising a doped single crystalline semiconductor material that is aligned to a single crystalline semiconductor structure of the horizontal channel portion; or
the source region, the drain region and the horizontal channel portion have a doping of the same first conductivity type, and the first vertical transistor channel portion is either intrinsic or has a doping of the first conductivity type.

4. The device of claim 1 , further comprising a shallow trench isolation structure comprising a dielectric material embedded in an upper portion of the substrate, wherein a bottom surface of the gate electrode contact structure contacts a top surface of the shallow trench isolation structure.

5. The device of claim 4 , further comprising a dielectric fill material portion vertically extending through each insulating layer in the first portion of the alternating stack and laterally surrounded by the gate electrode contact structure.

6. The device of claim 5 , further comprising a bottom active region contact structure extending through the first portion of the alternating stack and contacting a top surface of the bottom active region.

7. The device of claim 6 , further comprising an insulating spacer laterally surrounding the bottom active region contact structure, contacting the bottom active region, and comprising a dielectric material having a same composition as the dielectric fill material portion.

8. The device of claim 1 , wherein the field effect transistor comprises:
a second vertical transistor channel portion extending through the first portion of the alternating stack;
a second gate dielectric laterally surrounding the second vertical transistor channel portion and surrounded by the electrically conductive layers; and
a second top active region overlying the respective second vertical transistor channel portion and electrically shorted to the first top active region.

9. The device of claim 8 , wherein the bottom active region is a common source region for the first and the second transistor channel portions.

10. The device of claim 1 , wherein:
the memory film comprises a tunneling dielectric laterally surrounding the memory device channel and charge storage regions laterally surrounding the tunneling dielectric;
the three-dimensional memory device comprises a three dimensional NAND device;
the field effect transistor comprises a word line switching transistor for the three dimensional NAND device;
the electrically conductive layers in the second portion of the stack comprise word lines of the three dimensional NAND device; and
at least one word line of the three dimensional NAND device is electrically connected by an interconnect to the source or drain region of the word line switching transistor.

11. The device of claim 10 , wherein:
the memory film has a same sequence of material layers as the first gate dielectric of the field effect transistor;
each material layer in the sequence of the memory film has a same thickness as a corresponding material layer in the first gate dielectric;
each memory device channel of the at least one memory structure and the first vertical transistor channel portion of the field effect transistor comprise a common first semiconductor material;
a memory drain region is located on top of each memory stack structure;
each memory drain region and the first top active region comprise a common second doped semiconductor material.

12. The device of claim 10 , wherein the memory film has a different sequence of material layers from the first gate dielectric of the field effect transistor.

13. The device of claim 1 , further comprising:
a shallow trench isolation structure comprising a dielectric material embedded in an upper portion of the substrate; and
a dielectric separator structure laterally separating the first portion of the alternating stack and the second portion of the alternating stack.

14. The device of claim 1 , wherein:
the three-dimensional memory device comprises a vertical NAND device formed in a memory region;
the electrically conductive layers in the second portion of the alternating stack comprise, or are electrically connected to a respective word line of the NAND device;
the memory region comprises:
a plurality of memory device channels, wherein at least one end portion of each of the plurality of memory device channels extends substantially perpendicular to a top surface of the substrate;
a plurality of charge storage regions, each charge storage region located adjacent to a respective one of the plurality of memory device channels; and
a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate;

the plurality of control gate electrodes comprise at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level;
the electrically conductive layers in the second portion of the alternating stack are in electrical contact with the plurality of control gate electrodes and extend from the memory region to a contact region including the plurality of electrically conductive via connections which are electrically connected to a source region of the field effect transistor; and
the substrate comprises a silicon substrate containing a driver circuit for the NAND device.

Assignees

• Sandisk Technologies Inc
• Sandisk Technologies Llc

Inventors

• Nishikawa Masatoshi
• Koketsu Hiroaki
• Toyama Fumiaki
• Oh Junji

Classifications

• H01L27/11556

  Electricity · mapped topic

• H01L27/1157

  Electricity · mapped topic

• H01L27/11524 Primary

  Electricity · mapped topic

• H01L27/11582

  Electricity · mapped topic

• H10D30/6735

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title