Mid-plane word line switch connection for CMOS under three-dimensional memory device and method of making thereof

Patent metadata

Field	Value
Publication number	US-9953992-B1
Application number	US-201715611220-A
Country	US
Kind code	B1
Filing date	Jun 1, 2017
Priority date	Jun 1, 2017
Publication date	Apr 24, 2018
Grant date	Apr 24, 2018

Abstract

A three-dimensional memory array device can include mid-plane terrace regions between a pair of memory array regions. The electrically conductive layers of the three-dimensional memory array device continuously extend between the pair of memory array regions through a connection region, which is provided adjacent to the mid-plane terrace regions. Contact via structures contacting the electrically conductive layers can be provided in the mid-plane terrace regions, and through-memory-level via structures that extend through the alternating stack and connected to underlying lower metal interconnect structures and semiconductor devices can be provided through the mid-plane terrace region and/or through the connection region. Upper metal interconnect structures can connect the contact via structures and the through-memory-level via structures.

First claim

What is claimed is:

1. A semiconductor structure comprising an alternating stack of insulating layers and electrically conductive layers located over a substrate, wherein the insulating layers and the electrically conductive layers within the alternating stack continuously extend into each of:
a first memory array region including first memory stack structures that extend through the alternating stack;
a second memory array region including second memory stack structures that extend through the alternating stack, wherein the second memory array region is laterally spaced from the first memory array region along a first horizontal direction;
a first terrace region adjoined to the first memory array region and including first stepped surfaces of the alternating stack;
a second terrace region adjoined to the second memory array region and including second stepped surfaces of the alternating stack and spaced from the first terrace region along the first horizontal direction, wherein the first terrace region and the second terrace region are located between the first memory array region and the second array region; and
a connection region within which each of the insulating layers and the electrically conductive layers within the alternating stack continuously extends between the first and second memory array regions.

2. The semiconductor structure of claim 1 , wherein a lateral separation distance along the first horizontal direction between the first stepped surfaces and the second stepped surfaces increases with a vertical distance from the substrate for the electrically conductive layers in the alternating stack.

3. The semiconductor structure of claim 1 , wherein:
the connection region is located between the first and the second memory array regions;
the connection region is laterally spaced from the first and second terrace regions along a second horizontal direction that is perpendicular to the first horizontal direction; and
each layer within the alternating stack has a same width along the second horizontal direction within the connection region.

4. The semiconductor structure of claim 3 , further comprising bit lines extending in the second horizontal direction, wherein:
the first memory array region, the second memory array region, the connection region and the first and the second terrace regions are located in a same memory plane;
the electrically conductive layers comprise word lines of a NAND memory device which extend in the first horizontal direction; and
each of the first and the second memory stack structures comprises a vertical semiconductor channel and a memory film.

5. The semiconductor structure of claim 4 , wherein:
a first portion of the first memory array region, a first portion of the second memory array region, the connection region and the first and the second terrace regions are located in a same first memory block; and
each of the insulating layers and the electrically conductive layers within the alternating stack continuously extends in the first horizontal direction between the first portion of the first memory array region and the first portion of the second memory array regions in the connection region in the first memory block.

6. The semiconductor structure of claim 1 , further comprising:
contact via structures contacting a top surface of a respective one of the electrically conductive layers within the first and second terrace regions; and
a retro-stepped dielectric material portion having a planar top surface and a pair of stepped bottom surfaces,

wherein:
a first stepped bottom surface of the retro-stepped dielectric material portion contacts the first stepped surfaces in the first terrace region;
a second stepped bottom surface of the retro-stepped dielectric material portion contacts the second stepped surfaces in the second terrace region; and
the contact via structures vertically extend through the retro-stepped dielectric material portion.

7. The semiconductor structure of claim 6 , further comprising:
semiconductor devices located on a substrate semiconductor layer of the substrate;
lower metal interconnect structures embedded in lower dielectric layers and electrically connected to, and located over, the semiconductor devices; and
through-memory-level via structures extending through the retro-stepped dielectric material portion and electrically shorted to a respective one of the lower metal interconnect structures.

8. The semiconductor structure of claim 7 , further comprising additional through-memory-level via structures extending through the alternating stack in the connection region and electrically shorted to a respective one of the lower metal interconnect structures.

9. The semiconductor structure of claim 8 , wherein:
the through-memory-level via structures extending through the retro-stepped dielectric material portion extend through less than all layers within the alternating stack;
each of the additional through-memory-level via structures extending through the alternating stack in the connection region extends through each layer within the alternating stack; and
each of the through-memory-level via structures extending through the retro-stepped dielectric material portion and each of the additional through-memory-level via structures are laterally isolated from the electrically conductive layers by a respective insulating liner.

10. The semiconductor structure of claim 7 , wherein a subset of the through-memory-level via structures is electrically shorted to a respective one of the electrically conductive layers through a respective one of the contact via structures.

11. The semiconductor structure of claim 1 , further comprising a pair of backside trenches laterally extending along the first horizontal direction and vertically extending from a bottommost layer of the alternating stack to a topmost layer of the alternating stack, wherein:
a first one of the pair of backside trenches has a sidewall that contacts a first subset of sidewalls of the alternating stack in the first memory array region, in the second memory array region, in the first terrace region, and in the second terrace region; and
a second one of the pair of backside trenches has a sidewall that contacts a second subset of sidewalls of the alternating stack in the first memory array region, in the second memory array region, in the connection region.

12. The semiconductor structure of claim 1 , wherein:
the semiconductor structure comprises a monolithic three-dimensional NAND memory device that comprises a first three-dimensional memory array located in the first memory array region and a second three-dimensional memory array located in the second memory array region;
the electrically conductive layers comprise, or are electrically connected to, a respective word line of the monolithic three-dimensional NAND memory device;
the substrate comprises a silicon substrate;
the first memory stack structures comprise a first array of monolithic three-dimensional NAND strings;
the second memory stack structures comprise a second array of monolithic three-dimensional NAND strings;
the silicon substrate contains an integrated circuit comprising a driver circuit for the monolithic three-dimensional NAND memory device located thereon;
the electrically conductive layers comprise a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate in the first and second memory array regions; and
each of the first and second arrays of monolithic three-dimensional NAND strings comprises:
a plurality of semiconductor channels, wherein at least one end portion

Assignees

• Sandisk Technologies Llc

Inventors

• Ogawa Hiroyuki
• Kai James

Classifications

• H01L27/11524 Primary

  Electricity · mapped topic

• H01L27/11573

  Electricity · mapped topic

• H01L27/11582

  Electricity · mapped topic

• H01L27/11529

  Electricity · mapped topic

• H01L27/11556

  Electricity · mapped topic