Semiconductor device including a capacitor structure and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-10475661-B2
Application number	US-201816021100-A
Country	US
Kind code	B2
Filing date	Jun 28, 2018
Priority date	Sep 18, 2017
Publication date	Nov 12, 2019
Grant date	Nov 12, 2019

Abstract

A method for manufacturing a semiconductor device includes providing a substrate structure. The method includes forming a lower sacrificial layer, a lower supporter layer, an upper sacrificial layer, and an upper supporter layer which are sequentially stacked on the substrate structure. The method includes forming a mask pattern on the upper supporter layer; forming an upper supporter pattern by etching the upper supporter layer using the mask pattern as an etch mask. The method includes forming a recess region penetrating the upper supporter pattern, the upper sacrificial layer, the lower supporter layer, and the lower sacrificial layer, and removing the lower sacrificial layer and the upper sacrificial layer. The mask pattern is removed during the process of forming the upper supporter pattern. And, when the process of forming the recess region ends, the upper supporter pattern remains.

First claim

What is claimed is:

1. A method for manufacturing a semiconductor device, the method comprising:
providing a substrate structure;
forming a lower sacrificial layer, a lower supporter layer, an upper sacrificial layer, and an upper supporter layer which are sequentially stacked on the substrate structure;
forming a mask pattern on the upper supporter layer;
forming an upper supporter pattern by etching the upper supporter layer using the mask pattern as an etch mask;
forming a recess region penetrating the upper supporter pattern, the upper sacrificial layer, the lower supporter layer, and the lower sacrificial layer; and
removing the lower sacrificial layer and the upper sacrificial layer,
wherein the mask pattern is removed during the process of forming the upper supporter pattern, and
wherein, when the process of forming the recess region is completed, the upper supporter pattern remains.

2. The method of claim 1 , further comprising:
forming a lower electrode pattern extending along an inner surface of the recess region.

3. The method of claim 2 , wherein the forming the lower electrode pattern comprises:
forming a lower electrode layer extending along an upper surface of the upper supporter pattern and the inner surface of the recess region; and
removing the lower electrode layer on the upper surface of the upper supporter pattern.

4. The method of claim 2 , further comprising:
forming an upper electrode layer on the lower electrode pattern; and
forming a dielectric layer between the lower electrode pattern and the upper electrode layer.

5. The method of claim 1 , wherein a thickness of the upper supporter pattern is reduced during the process of forming the recess region.

6. The method of claim 1 , wherein the forming the recess region comprises sequentially etching the upper sacrificial layer, the lower supporter layer, and the lower sacrificial layer using the upper supporter pattern as an etch mask.

7. The method of claim 6 , wherein the forming the recess region further comprises performing a first cleaning process laterally enlarging the recess region in the upper sacrificial layer, and
wherein the first cleaning process is performed before the process of etching the lower supporter layer.

8. The method of claim 6 , wherein the forming the recess region further comprises performing a second cleaning process laterally enlarging the recess region in the lower sacrificial layer, and
wherein the second cleaning process is performed after the process of etching the lower sacrificial layer.

9. A method for manufacturing a semiconductor device, the method comprising:
providing a substrate structure;
forming a sacrificial layer and a supporter layer stacked sequentially on the substrate structure;
forming a mask pattern on the supporter layer;
forming a supporter pattern by etching the supporter layer using the mask pattern as an etch mask;
forming the sacrificial pattern by etching the sacrificial layer using the supporter pattern as an etch mask; and
removing the sacrificial pattern,
wherein the mask pattern is removed during the process of forming the supporter pattern, and
wherein, when the process of forming the sacrificial pattern is completed, the supporter pattern remains.

10. The method of claim 9 , wherein the sacrificial layer includes a carbon layer doped with impurities, and
wherein the impurities include an element different from carbon.

11. The method of claim 10 , wherein the impurities are uniformly distributed in the sacrificial pattern, and
wherein a concentration of the impurities ranges from 20 vol % to 80 vol % in the sacrificial pattern.

12. The method of claim 10 , wherein the impurities include boron (B) or tungsten (W).

13. The method of claim 10 , wherein a concentration of the impurities has a gradient in the sacrificial pattern, and
wherein the concentration of the impurities becomes progressively higher toward the substrate structure or becomes progressively lower toward the substrate structure.

14. The method of claim 9 , wherein the supporter pattern includes silicon (Si), silicon oxide, a metal oxide, or silicon oxynitride.

15. The method of claim 9 , wherein the etching the sacrificial layer is performed by a dry plasma etching process using an etching gas including a Cl 2 gas.

16. The method of claim 15 , wherein the etching gas further includes an O 2 gas, a HBr gas, and a carbon oxysulfide (COS) gas.

17. A method for manufacturing a semiconductor device, the method comprising:
forming a first sacrificial layer, a first supporter layer, a second sacrificial layer and a plurality of second supporter patterns above a substrate;
etching the first sacrificial layer, the first supporter layer and the second sacrificial layer by using the plurality of second supporter patterns as a mask to form a plurality of first sacrificial patterns, a plurality of first supporter patterns and a plurality of second sacrificial patterns, wherein a thickness of each of the second supporter patterns is reduced by the etching, and wherein the etching forms a plurality of recess regions between the plurality of first sacrificial patterns, the plurality of first supporter patterns, the plurality of second sacrificial patterns and the plurality of second supporter patterns;
forming a capacitor in each of the recess regions of the plurality of recess regions, wherein the capacitor includes a first conductive pattern, a dielectric pattern on the first conductive pattern and a second conductive pattern on the dielectric pattern, and wherein at least two second supporter patterns of the plurality of second supporter patterns are positioned to support the capacitor formed in each of the recess regions; and
removing the plurality of first sacrificial patterns and the plurality of second sacrificial patterns.

18. The method of claim 17 , wherein the plurality of first sacrificial patterns and the plurality of second sacrificial patterns are removed after forming the first conductive pattern and before forming the dielectric pattern and the second conductive pattern.

19. The method of claim 17 , wherein the forming the plurality of the second supporter patterns comprising:
forming a second supporter layer on the second sacrificial layer;
forming a plurality of mask patterns on the second supporter layer; and
etching the second supporter layer using the plurality of mask patterns as an etch mask,
wherein the plurality of the mask patterns are removed during the process of etching the second supporter layer.

20. The method of claim 17 , wherein each of the first sacrificial layer and the second sacrificial layer include a carbon layer doped with impurities, and
wherein the impurities include an element different from carbon.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Seo Youngsik
• Cho Sungil

Classifications

• H10P70/20

  Cleaning during device manufacture · CPC title

• H10P50/287

  by chemical means · CPC title

• H10P50/285 Primary

  of materials not containing Si, e.g. PZT or Al2O3 · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H10P14/6339

  deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD · CPC title