Double patterning strategy for contact hole and trench in photolithography

Patent metadata

Field	Value
Publication number	US-9323155-B2
Application number	US-201414294315-A
Country	US
Kind code	B2
Filing date	Jun 3, 2014
Priority date	Nov 30, 2007
Publication date	Apr 26, 2016
Grant date	Apr 26, 2016

Abstract

A method of lithography patterning includes forming a first resist pattern on a substrate, wherein the first resist pattern including a plurality of openings. A second resist pattern is formed on the substrate and within the plurality of openings of the first resist pattern, wherein the second resist pattern includes at least one opening therein on the substrate. The first resist pattern is removed to uncover the substrate underlying the first resist pattern.

First claim

What is claimed is:

1. A method comprising:
forming a material layer on a substrate;
forming a first resist pattern over the material layer, the first resist pattern having an opening therein;
baking the first resist pattern to form a baked resist pattern;
forming a second resist layer within the opening of the baked resist pattern, wherein the baked resist pattern is insoluble in the second resist layer;
patterning the second resist layer to form a second resist pattern; and
removing the baked resist pattern; and
after removing the baked resist pattern, removing portions of the material layer using the second resist pattern as a mask.

2. The method of claim 1 , wherein the first resist pattern includes a first positive resist material.

3. The method of claim 2 , wherein the second resist pattern includes a second positive resist material.

4. The method of claim 1 , wherein the opening exposes a portion of the material layer.

5. The method of claim 1 , wherein the material layer is formed of a material selected from the group consisting of a dielectric material and a conductive material.

6. The method of claim 1 , further comprising forming a mask layer on the material layer.

7. The method of claim 6 , wherein forming the first resist pattern over the material layer includes forming the first resist pattern directly on the mask layer.

8. The method of claim 1 , wherein forming the second resist layer within the opening of the baked resist pattern include forming the second resist layer in the opening such that a top surface of the second resist layer is lower than a top surface of the baked resist pattern, the top surface of the second resist layer and the top surface of the baked resist pattern facing away from the substrate.

9. A method comprising:
forming a material layer over a substrate;
forming a first resist pattern over the material layer, the first resist pattern having an opening therein that exposes a portion of the material layer;
baking the first resist pattern to form a baked resist pattern;
forming a second resist layer in the opening of the baked resist pattern;
exposing the second resist layer to form an exposed feature and an unexposed feature in the second resist layer; and
removing the exposed feature to form a second resist pattern;
removing the baked resist pattern; and
after removing the baked resist pattern, removing portions of the material layer using the second resist pattern as a mask.

10. The method of claim 9 , wherein removing the exposed feature includes applying a developer solvent to remove the exposed feature, leaving the unexposed feature on the substrate; and
wherein removing the baked resist pattern applying an etching process to selectively remove the baked resist pattern relative to the unexposed feature.

11. The method of claim 10 , wherein removing portions of the material layer using the second resist pattern as a mask includes etching the material layer using the second resist pattern as an etch mask to form a patterned material layer.

12. The method of claim 11 , further comprising:
removing the second resist pattern; and
after removing the second resist pattern, etching the substrate using the patterned material layer as an etch mask.

13. The method of claim 9 , wherein the material layer includes a conductive material.

14. The method of claim 9 , wherein removing the exposed feature to form the second resist pattern and removing the baked resist pattern occurs during the same developing process.

15. A method comprising:
forming a first resist pattern over a substrate, the first resist pattern having an opening therein;
baking the first resist pattern to form a baked resist pattern;
forming a second resist layer within the opening of the baked resist pattern, wherein the baked resist pattern is insoluble in the second resist layer;
patterning the second resist layer to form a second resist pattern; and
removing the baked resist pattern, and
after removing the baked resist pattern, removing portions of a material layer disposed over the substrate using the second resist pattern as a mask, and
wherein the first resist pattern and the second resist pattern include the same tone of photoresist.

16. The method of claim 15 , wherein the material layer is an antireflective coating layer, the method further comprising:
forming a hard mask layer over the substrate prior to forming the first resist pattern over the substrate; and
forming an antireflective coating layer over the hard mask layer prior to forming the first resist pattern over the substrate.

17. The method of claim 16 , wherein removing portions of the material layer disposed over the substrate using the second resist pattern as the mask includes etching the antireflective coating layer and the hard mask layer using the second resist pattern as an etch mask to form a patterned antireflective coating layer and a patterned hard mask layer.

18. The method of claim 17 , further comprising:
removing the second resist pattern and the patterned antireflective coating layer; and
after removing the second resist pattern and the patterned antireflective coating layer, etching the substrate using the patterned hard mask layer as an etch mask.

19. The method of claim 15 , wherein a top surface of the second resist layer is lower than a top surface of the baked resist pattern.

20. The method of claim 15 , wherein the first resist pattern and the second resist pattern include a positive tone resist material.

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Chen Chun-Kuang
• Yeh Hsiao-Wei
• Lin Chih-An
• Wang Chien-Wei
• Hsu Feng-Cheng

Classifications

• H10P76/4085

  characterised by the processes involved to create the masks · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• G03F7/0035 Primary

  Multiple processes, e.g. applying a further resist layer on an already in a previously step, processed pattern or textured surface · CPC title

• G03F7/38 Primary

  Treatment before imagewise removal, e.g. prebaking {(G03F7/265 takes precedence)} · CPC title

• G03F7/40

  Treatment after imagewise removal, e.g. baking · CPC title