Methods of manufacturing semiconductor device

Patent metadata

Field	Value
Publication number	US-2016104618-A1
Application number	US-201514715631-A
Country	US
Kind code	A1
Filing date	May 19, 2015
Priority date	Oct 10, 2014
Publication date	Apr 14, 2016
Grant date	—

Abstract

A method of manufacturing a semiconductor device is provided. The method includes forming a molding layer and a supporter layer on a semiconductor substrate, forming a multiple mask layer including a first mask layer and a second mask layer formed on the first mask layer, on the supporter layer. The first mask layer is formed of a material having an etch selectivity with respect to the molding layer and the second mask layer is formed of a material having an etch selectivity with respect to the supporter layer. The method includes forming a first mask pattern and a second mask pattern formed on the first mask pattern by patterning the multiple mask layer, etching the supporter layer by performing a first etching process using the second mask pattern as an etch mask, etching the molding layer, and forming a hole by performing a second etching process using the first mask pattern as an etch mask.

First claim

What is claimed is:

1 . A method of manufacturing a semiconductor device, comprising:
forming a molding layer and a supporter layer on a semiconductor substrate; forming a multiple mask layer including a first mask layer and a second mask layer formed on the first mask layer, on the supporter layer, wherein the first mask layer comprises a first material having a first etch selectivity with respect to the molding layer, and wherein the second mask layer comprises a second material having a second etch selectivity with respect to the supporter layer; patterning the multiple mask layer to form a first mask pattern and a second mask pattern on the first mask pattern; performing a first etching process using the second mask pattern as an etch mask to etch the supporter layer; and performing a second etching process using the first mask pattern as an etch mask to etch the molding layer and form a hole.

2 . The method of claim 1 , further comprising:
forming a storage electrode in the hole; patterning the supporter layer to form a supporter pattern; removing the molding layer to expose the storage electrode and the supporter pattern; conformally forming a dielectric layer on the storage electrode and the supporter pattern; and forming a plate electrode on the dielectric layer.

3 . The method of claim 1 , wherein the second mask pattern is etched and removed during the first etching process.

4 . The method of claim 1 , further comprising removing the first mask pattern after completing the second etching process.

5 . The method of claim 1 , wherein the first mask layer comprises a metal nitride.

6 . The method of claim 5 , wherein the second mask layer comprises silicon.

7 . The method of claim 6 , wherein the second mask layer further comprises polysilicon.

8 . The method of claim 1 , wherein the molding layer comprises silicon oxide and the supporter layer comprises silicon nitride.

9 . The method of claim 8 , further comprising:
forming a buffer layer between the supporter layer and the first mask layer, wherein the buffer layer is etched during the first etching process.

10 . A method of manufacturing a semiconductor device, comprising:
forming a lower molding layer, a lower supporter layer, an upper molding layer, and an upper supporter layer on a semiconductor substrate; forming a multiple mask layer including a first mask layer, a second mask layer, a third mask layer, and a fourth mask layer, which are sequentially stacked on the upper supporter layer; patterning the multiple mask layer to form a first mask pattern, a second mask pattern, a third mask pattern, and a fourth mask pattern, which are stacked; performing a first etching process using the fourth mask pattern as an etch mask to etch the upper supporter layer; performing a second etching process using the third mask pattern as an etch mask to etch the upper molding layer; performing a third etching process using the second mask pattern as an etch mask to etch the lower supporter layer; and performing a fourth etching process using the first mask pattern as an etch mask to etch the lower molding layer and form a hole.

11 . The method of claim 10 , wherein the first and third mask layers each comprise a metal nitride.

12 . The method of claim 10 , wherein the second and fourth mask layers each comprise polysilicon.

13 . The method of claim 10 , wherein the molding layer comprises silicon oxide and the supporter layer comprises silicon nitride.

14 . The method of claim 10 , further comprising:
forming a storage electrode in the hole; patterning the upper supporter layer to form a supporter pattern; removing the upper molding layer, the lower supporter layer, and the lower molding layer and exposing the storage electrode and the supporter pattern; conformally forming a dielectric layer on the storage electrode and the supporter pattern; and forming a plate electrode on the dielectric layer.

15 . The method of claim 14 , wherein the removing of the upper molding layer, the lower supporter layer, and the lower molding layer comprises removing the upper molding layer and the lower molding layer, and patterning the lower supporter layer to be aligned with the supporter pattern.

16 . A method of manufacturing a semiconductor device, comprising:
forming a molding layer on a semiconductor substrate; forming a supporter layer on the molding layer; forming a first mask layer, having a first etch selectivity with respect to the molding layer, on the supporter layer; forming a second mask layer, having a second etch selectivity, different from the first etch selectivity, with respect to the supporter layer, on the first mask layer; performing a first etching process using a first etchant to etch the supporter layer, wherein the second mask layer is used as an etch mask for the first etching process; and performing a second etching process using a second etchant to etch the molding layer, wherein the first mask layer is used as an etch mask for the second etching process.

17 . The method of claim 16 ,
wherein the first mask layer comprises a thickness h1 and the second mask layer comprises a thickness h2, wherein the thickness h1 is less than the thickness h2, and wherein the second mask layer comprises polysilicon and the first mask layer comprises a metal nitride.

18 . The method of claim 16 ,
wherein the molding layer comprises silicon oxide, and the supporter layer comprises silicon nitride.

19 . The method of claim 16 , further comprising:
forming a buffer layer between the supporter layer and the first mask layer, wherein the buffer layer is etched during the first etching process.

20 . The method of claim 16 ,
wherein the first etchant used by the first etch process to etch the supporter layer comprises CHF 3 and/or CH 2 F 2 , and wherein the second etchant used by the second etch process to etch the molding layer comprises C 4 F 8 and/or C 4 F 6 .

Assignees

• Samsung Electronics Co Ltd

Inventors

• Hong Hyun-Sil
• Cho Sungil

Classifications

• H10P76/408

  characterised by their sizes, orientations, dispositions, behaviours or shapes · CPC title

• H10P50/283

  by chemical means · CPC title

• H10P50/73 Primary

  using masks for insulating materials · CPC title

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title