Semiconductor device including a capacitor and a method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9496266-B2
Application number	US-201514595834-A
Country	US
Kind code	B2
Filing date	Jan 13, 2015
Priority date	Jul 18, 2014
Publication date	Nov 15, 2016
Grant date	Nov 15, 2016

Abstract

A method of manufacturing a semiconductor device is provided. The method includes sequentially forming a mold layer and a preliminary support layer on a substrate, forming a plurality of lower electrodes through the preliminary support layer and the mold layer, removing a portion of the preliminary support layer between the plurality of lower electrodes to form a preliminary support layer pattern having an open area exposing a top surface of the mold layer, removing the mold layer to form a void between the substrate and the preliminary support layer pattern, filling the open area and the void with a sacrificial layer, and replacing the preliminary support layer pattern with a support pattern.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, the method comprising:
sequentially forming a mold layer and a preliminary support layer on a substrate;
forming a plurality of lower electrodes through the preliminary support layer and the mold layer;
removing a portion of the preliminary support layer between the plurality of lower electrodes to form a preliminary support layer pattern having an open area exposing a top surface of the mold layer;
removing the mold layer to form a void between the substrate and the preliminary support layer pattern;
filling the open area and the void with a sacrificial layer; and
replacing the preliminary support layer pattern with a support pattern.

2. The method of claim 1 , wherein replacing the preliminary support layer pattern with the support pattern includes:
removing the preliminary support layer pattern to expose a top surface of the sacrificial layer;
forming a support layer on the exposed top surface of the sacrificial layer; and
planarizing the support layer until a top surface of the lower electrode is exposed to form the support pattern on the exposed top surface of the sacrificial layer.

3. The method of claim 1 , further comprising:
removing the sacrificial layer to expose the plurality of lower electrodes; and
sequentially forming a dielectric layer and an upper electrode on the plurality of lower electrodes.

4. The method of claim 1 , wherein top surfaces of the lower electrodes are formed to be substantially coplanar with a top surface of the support pattern.

5. The method of claim 1 , wherein the support pattern includes a first material different from that of the preliminary support layer pattern, and the first material includes an oxide.

6. The method of claim 1 , wherein the mold layer includes a semiconductor oxide, polysilicon, amorphous silicon, silicon-germanium or a combination thereof, and
wherein the sacrificial layer includes spin on hardmask (SOH) and/or polysilicon.

7. The method of claim 1 , wherein each of the plurality of lower electrodes is formed to have a cylindrical shape and/or a pillar shape.

8. The method of claim 1 , wherein replacing the preliminary support layer pattern with the support pattern includes:
removing the preliminary support layer pattern to expose a portion of the sacrificial layer;
partially removing the exposed portion of the sacrificial layer to form a recess; and
sequentially forming a first support pattern, an additional sacrificial layer, and a second support pattern in the recess.

9. The method of claim 8 , wherein the first support pattern includes an oxide and/or a nitride, and wherein the second support pattern includes an oxide.

10. The method of claim 1 , further comprising:
sequentially forming an additional mold layer and an additional preliminary support layer on the support pattern and the sacrificial layer;
forming a plurality of additional lower electrodes through the additional preliminary support layer and the additional mold layer to contact the plurality of lower electrodes, respectively;
removing a portion of the additional preliminary support layer between the plurality of additional lower electrodes to form an additional preliminary support layer pattern having an additional open area exposing a top surface of the additional mold layer;
removing the additional mold layer to form an additional void between the support pattern and the additional preliminary support layer pattern;
filling the additional open area and the additional void with an additional sacrificial layer;
replacing the additional preliminary support layer pattern with an additional support pattern;
removing the sacrificial layer and the additional sacrificial layer to expose the plurality of lower electrodes and the plurality of additional lower electrodes; and
sequentially forming a dielectric layer and an upper electrode on the plurality of lower electrodes and the plurality of additional lower electrodes.

11. The method of claim 10 , wherein each of the plurality of lower electrodes is formed to have a cylindrical shape or a pillar shape, and wherein each of the plurality of additional lower electrodes is formed to have a cylindrical shape or a pillar shape.

12. The method of claim 10 , wherein the support pattern includes an oxide and/or a nitride, and wherein the additional support pattern includes a first material different from that of the preliminary support layer pattern, and the first material includes an oxide.

13. The method of claim 10 , wherein top surfaces of the additional lower electrodes are formed to be substantially coplanar with a top surface of the additional support pattern.

14. The method of claim 10 , wherein the additional mold layer includes a semiconductor oxide, polysilicon, amorphous silicon, silicon-germanium or a combination thereof, and
wherein the additional sacrificial layer includes spin on hardmask (SOH) and/or polysilicon.

15. The method of claim 1 , further comprising forming an additional support pattern between the substrate and the support pattern.

16. The method of claim 15 , wherein the support pattern includes an oxide, and the additional support pattern includes an oxide and/or a nitride, and
wherein top surfaces of the lower electrodes are formed to be substantially coplanar with a top surface of the support pattern.

17. A method of manufacturing a semiconductor device, the method comprising:
forming a plurality of electrode structures on a substrate, each of the electrode structures extending in a first direction substantially perpendicular to a top surface of the substrate; and
forming a support pattern structure between the plurality of electrode structures, the support pattern structure including a first support pattern and a second support pattern, the support pattern structure contacting at least a portion of each of the electrode structures,
wherein the first support pattern is apart by a first distance from the top surface of the substrate in the first direction, and the second support pattern is apart by a second distance from the top surface of the substrate in the first direction, the second distance being greater than the first distance,
wherein the second support pattern includes an oxide,
wherein the second support pattern has a top surface substantially coplanar with at least one of the electrode structures,
wherein a length of a portion of the first support pattern between neighboring electrode structures is greater than that of a portion of the second support pattern between the neighboring electrode structures, and
wherein a width of an upper portion of each of the electrode structures is greater than that of a lower portion of each of the electrode structures.

18. The method of claim 17 , wherein each of the plurality of electrode structures is formed to have a cylindrical shape, a pillar shape, or a combination shape of the cylindrical shape and the pillar shape.

19. The method of claim 17 , wherein forming the plurality of electrode structures includes forming first and second electrode structures at third and fourth distances, respectively, from the top surface of the substrate in the first direction, the fourth distance being greater than the third distance, and the second electrode structure contacting at least a portion of a top surface of the first electrode structure,
wherein a top surface of the first support pattern is substantially coplanar with that of the first electrode structure, and a top surface of the sec

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Kyung-Eun
• Cho Young-Seung
• Park So-Hyun
• Yun Sang-Jo

Classifications

• H10B99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10B12/315 Primary

  with the capacitor higher than a bit line · CPC title

• H10B12/033 Primary

  the capacitor extending over the transistor · CPC title

• H10D1/716 Primary

  having vertical extensions · CPC title

• H10D1/692

  Electrodes · CPC title