Mating backplane for high speed, high density electrical connector

Patent metadata

Field	Value
Publication number	US-10455689-B2
Application number	US-201816032284-A
Country	US
Kind code	B2
Filing date	Jul 11, 2018
Priority date	Nov 21, 2014
Publication date	Oct 22, 2019
Grant date	Oct 22, 2019

Abstract

A printed circuit board includes a plurality of layers including attachment layers and routing layers; and via patterns formed in the plurality of layers, each of the via patterns including first and second signal vias forming a differential signal pair, the first and second signal vias extending through at least the attachment layers; ground vias extending through at least the attachment layers, the ground vias including ground conductors; and shadow vias located adjacent to each of the first and second signal vias, wherein the shadow vias are free of conductive material in the attachment layers. The printed circuit board may further include slot vias extending through the attachment layers and located between via patterns.

First claim

What is claimed is:

1. A printed circuit board comprising:
a plurality of layers including conductive layers separated by dielectric layers;
first and second signal vias forming a differential signal pair, the first and second signal vias extending through one or more of the plurality of layers; and
shadow vias associated with each of the signal vias, the shadow vias extending through one or more of the plurality of layers, wherein the shadow vias have a first diameter above a predetermined depth in the plurality of layers and a second diameter, different from the first diameter, below the predetermined depth in the plurality of layers.

2. The printed circuit board as defined in claim 1 , wherein the shadow vias include shadow vias located on opposite sides of each of the first and second signal vias.

3. The printed circuit board as defined in claim 1 , wherein the shadow vias include shadow vias located on a line through the first and second signal vias.

4. The printed circuit board as defined in claim 1 , further comprising ground vias extending through one or more of the plurality of layers.

5. The printed circuit board as defined in claim 1 , wherein the shadow vias are free of conductive material in one or more of the plurality of layers.

6. The printed circuit board as defined in claim 1 , wherein the shadow vias are plated or filled with a conductive material.

7. The printed circuit board as defined in claim 1 , wherein the shadow vias include conductive material that interconnects ground planes of two or more of the plurality of layers.

8. The printed circuit board as defined in claim 1 , wherein the shadow vias are free of conductive material to a predetermined depth in the plurality of layers.

9. The printed circuit board as defined in claim 1 , wherein the shadow vias include shadow vias located on opposite sides of the first and second signal vias and additional shadow vias located on a line through the first and second signal vias.

10. The printed circuit board as defined in claim 1 , wherein the shadow vias have smaller diameters than the first and second signal vias in one or more layers of the plurality of layers.

11. A method for making a printed circuit board, comprising:
forming a plurality of layers including conductive layers separated by dielectric layers;
forming first and second signal vias extending through one or more of the plurality of layers; and
forming shadow vias associated with each of the first and second signal vias, the shadow vias extending through one or more of the plurality of layers, wherein forming shadow vias includes forming the shadow vias with a first diameter above a predetermined depth in the plurality of layers and forming the shadow vias with a second diameter, different from the first diameter, below the predetermined depth in the plurality of layers.

12. The method as defined in claim 11 , wherein forming shadow vias includes forming shadow vias located on opposite sides of each of the first and second signal vias.

13. The method as defined in claim 11 , wherein forming shadow vias includes forming shadow vias located on a line through the first and second signal vias.

14. The method as defined in claim 11 , wherein forming shadow vias includes forming shadow vias that are free of conductive material.

15. The method as defined in claim 11 , wherein forming shadow vias includes forming shadow vias that are plated or filled with a conductive material.

16. The method as defined in claim 11 , wherein forming shadow vias includes forming shadow vias with conductive material that interconnects two or more of the plurality of layers.

17. The method as defined in claim 11 , wherein forming shadow vias includes forming shadow vias free of conductive material to a predetermined depth in the plurality of layers.

18. The method as defined in claim 11 , wherein forming shadow vias includes forming shadow vias located on opposite sides of the first and second signal vias and forming additional shadow vias located on a line through the first and second signal vias.

19. The method as defined in claim 11 , further comprising forming ground vias extending through one or more of the plurality of layers.

20. The method as defined in claim 11 , wherein the shadow vias are formed with smaller diameters than the first and second signal vias in one or more layers of the plurality of layers.

Assignees

• Amphenol Corp

Inventors

• Gailus Mark W
• Cartier Jr Marc B
• Sivarajan Vysakh
• Levine David

Classifications

• H05K1/0219 Primary

  Printed shielding conductors for shielding around or between signal conductors, e.g. coplanar or coaxial printed shielding conductors · CPC title

• H05K2201/09063

  Holes or slots in insulating substrate not used for electrical connections · CPC title

• H05K3/0047

  Drilling of holes · CPC title

• H05K2201/09318

  Core having one signal plane and one power plane · CPC title

• H05K1/115

  Via connections; Lands around holes or via connections (H05K1/112 takes precedence) · CPC title