Mating backplane for high speed, high density electrical connector

Patent metadata

Field	Value
Publication number	US-2016150645-A1
Application number	US-201514947166-A
Country	US
Kind code	A1
Filing date	Nov 20, 2015
Priority date	Nov 21, 2014
Publication date	May 26, 2016
Grant date	—

Abstract

A printed circuit board includes a plurality of layers including attachment layers and routing layers; and via patterns formed in the plurality of layers, each of the via patterns including first and second signal vias forming a differential signal pair, the first and second signal vias extending through at least the attachment layers; ground vias extending through at least the attachment layers, the ground vias including ground conductors; and shadow vias located adjacent to each of the first and second signal vias, wherein the shadow vias are free of conductive material in the attachment layers. The printed circuit board may further include slot vias extending through the attachment layers and located between via patterns.

First claim

What is claimed is:

1 . A printed circuit board comprising:
a plurality of layers including attachment layers and routing layers; signal vias extending through at least the attachment layers, the signal vias including signal conductors; ground vias extending through at least the attachment layers, the ground vias including ground conductors; and slot vias extending through the attachment layers, the slot vias including slot conductors that interconnect ground planes of two or more of the attachment layers.

2 . The printed circuit board as defined in claim 1 , wherein the signal vias comprise pairs of differential signal vias.

3 . The printed circuit board as defined in claim 2 , further comprising shadow vias located between the pairs of differential signal vias and the slot vias.

4 . The printed circuit board as defined in claim 1 , wherein the slot vias comprise contoured slots extending through only the attachment layers.

5 . The printed circuit board as defined in claim 2 , wherein the slot vias are located between adjacent pairs of differential signal vias.

6 . The printed circuit board as defined in claim 1 , wherein the slot vias extend through the attachment layers and interconnect ground planes of each of the attachment layers.

7 . The printed circuit board as defined in claim 3 , wherein the shadow vias include conductive material only in the routing layers.

8 . A printed circuit board comprising:
a plurality of layers including attachment layers and routing layers; signal vias extending through at least the attachment layers, the signal vias including signal conductors; ground vias extending through at least the attachment layers, the ground vias including ground conductors; and groups of blind plated vias extending through the attachment layers, the blind plated vias including conductors that interconnect ground planes of two or more of the attachment layers.

9 . The printed circuit board as defined in claim 8 , wherein the signal vias comprise pairs of differential signal vias.

10 . The printed circuit board as defined in claim 9 , further comprising shadow vias located between pairs of differential signal vias and the blind plated vias.

11 . The printed circuit board as defined in claim 8 , wherein the blind plated vias extend through only the attachment layers.

12 . The printed circuit board as defined in claim 9 , wherein the blind plated vias are located between adjacent pairs of differential signal vias.

13 . The printed circuit board as defined in claim 9 , wherein the ground vias comprise pairs of ground vias on opposite ends of the pairs of differential signal vias.

14 . The printed circuit board as defined in claim 9 , wherein the ground vias comprise slots on opposite ends of the pairs of differential signal vias.

15 . The printed circuit board as defined in claim 8 , wherein the blind plated vias extend through the attachment layers and interconnect the ground planes of each of the attachment layers.

16 . A printed circuit board comprising:
a plurality of layers including attachment layers and routing layers; and
via patterns formed in the plurality of layers, each of the via patterns comprising:
first and second signal vias forming a differential signal pair, the first and second signal vias extending through at least the attachment layers;
ground vias extending through at least the attachment layers, the ground vias including ground conductors; and
shadow vias located adjacent to each of the first and second signal vias, wherein the shadow vias are free of conductive material in the attachment layers.

17 . The printed circuit board as defined in claim 16 , wherein the shadow vias are located on opposite sides of each of the first and second signal vias.

18 . The printed circuit board as defined in claim 17 , wherein the shadow vias include conductive material in at least one of the routing layers.

19 . The printed circuit board as defined in claim 16 , wherein ground planes of the attachment layers are removed around and between the first and second signal vias to form antipads.

20 . The printed circuit board as defined in claim 19 , wherein the shadow vias are located at edges of the antipads.

21 . The printed circuit board as defined in claim 16 , wherein each of the via patterns further comprises additional shadow vias located adjacent to the first and second signal vias and spaced from the first and second signal vias in a direction of a line passing through the first and second signal vias.

22 . The printed circuit board as defined in claim 16 , further comprising slot vias between adjacent via patterns.

23 . The printed circuit board as defined in claim 22 , wherein the slot vias extend through the attachment layers and include slot conductors that interconnect the ground planes of two or more of the attachment layers.

24 . The printed circuit board as defined in claim 21 , wherein the additional shadow vias are located along the line passing through the first and second signal vias.

Assignees

• Amphenol Corp

Inventors

• Gailus Mark W
• Cartier Jr Marc B
• Sivarajan Vysakh
• Levine David

Classifications

• H05K3/4038

  Through-connections; Vertical interconnect access [VIA] connections (H05K3/403, H05K3/42 take precedence) · CPC title

• H05K2201/09718

  Clearance holes · CPC title

• H01R43/205 Primary

  with a panel or printed circuit board · CPC title

• H05K2201/09318

  Core having one signal plane and one power plane · CPC title

• H05K2201/09063

  Holes or slots in insulating substrate not used for electrical connections · CPC title