Mating backplane for high speed, high density electrical connector

Patent metadata

Field	Value
Publication number	US-9775231-B2
Application number	US-201514947091-A
Country	US
Kind code	B2
Filing date	Nov 20, 2015
Priority date	Nov 21, 2014
Publication date	Sep 26, 2017
Grant date	Sep 26, 2017

Abstract

A printed circuit board includes a plurality of layers including attachment layers and routing layers; and via patterns formed in the plurality of layers, each of the via patterns comprising: dual diameter first and second signal vias forming a differential signal pair, the first and second signal vias being configured to accept contact tails of signal conductors of a connector; dual diameter ground shadow vias adjacent to each of the first and second signal vias, wherein the dual diameter shadow ground vias have a reversed diameter configuration with respect to the dual diameter first and second signal vias; and ground vias configured to accept contact tails of ground conductors of the connector.

First claim

What is claimed is:

1. A printed circuit board comprising:
a plurality of layers including attachment layers and routing layers; and
via patterns formed in the plurality of layers, each of the via patterns comprising:
first and second signal vias forming a differential signal pair, the first and second signal vias each being configured with a first section having a first diameter and a second section having a second diameter, less than the first diameter; and
ground shadow vias adjacent to each of the first and second signal vias, the ground shadow vias each comprising a first section having a third diameter and a second section having a fourth diameter.

2. The printed circuit board as defined in claim 1 , wherein:
the first sections of the first and second signal vias are disposed in a first region of the plurality of layers;
the second sections of the first and second signal vias are disposed in a second region of the plurality of layers;
the first sections of the ground shadow vias are disposed in the first region of the plurality of layers;
the second sections of the ground shadow vias are disposed in the second region of the plurality of layers; and
the fourth diameter of each of the ground shadow vias is greater than the third diameter of each of the ground shadow vias.

3. The printed circuit board as defined in claim 2 , wherein the second diameter of each of the first and second signal vias is equal to the third diameter of each of the ground shadow vias.

4. The printed circuit board as defined in claim 2 , wherein the first diameter of each of the first and second signal vias is equal to the fourth diameter of each of the ground shadow vias.

5. The printed circuit board as defined in claim 2 , wherein a length of the first section of each of the first and second signal vias is equal to a length of the first section of each of the ground shadow vias.

6. The printed circuit board as defined in claim 1 , wherein each of the ground shadow vias is plated through or filled with a conductive material.

7. The printed circuit board as defined in claim 1 , wherein each of the ground shadow vias is a through via that extends through the plurality of layers.

8. The printed circuit board as defined in claim 2 , wherein the first region of the plurality of layers comprises the attachment layers and wherein the second region of the plurality of layers comprises the routing layers.

9. The printed circuit board as defined in claim 8 , wherein each of the first and second signal vias extends to a breakout layer of the routing layers for connection to a signal trace.

10. The printed circuit board as defined in claim 1 , wherein the ground shadow vias include ground shadow vias on opposite sides of each of the first and second signal vias.

11. The printed circuit board as defined in claim 1 , wherein the ground shadow vias are electrically connected to one or more ground planes of the plurality of layers.

12. The printed circuit board as defined in claim 2 , wherein the first section of each of the first and second signal vias and the first section of each of the ground shadow vias extend through the attachment layers of the plurality of layers.

13. The printed circuit board as defined in claim 1 , wherein each of the via patterns further comprises ground vias configured to accept contact tails of ground conductors of a connector.

14. The printed circuit board as defined in claim 1 , wherein the ground planes include at least one antipad around the first and second signal vias.

15. The printed circuit board as defined in claim 1 , wherein the first and second signal vias and the ground shadow vias are configured to provide impedance matching.

16. The printed circuit board as defined in claim 1 , wherein the ground shadow vias are configured to provide shielding between the differential signal pairs of adjacent via patterns.

17. The printed circuit board as defined in claim 1 , wherein a transition between the first and second diameters of the first and second signal vias occurs at a different level in the plurality of layers than a transition between the third and fourth diameters of the ground shadow vias.

18. A printed circuit board comprising:
a plurality of layers including attachment layers and routing layers; and
via patterns formed in the plurality of layers, each of the via patterns comprising:
dual diameter first and second signal vias forming a differential signal pair, the first and second signal vias being configured to accept contact tails of signal conductors of a connector;
dual diameter ground shadow vias adjacent to each of the first and second signal vias, wherein the dual diameter shadow ground vias have a reversed diameter configuration with respect to the dual diameter first and second signal vias; and
ground vias configured to accept contact tails of ground conductors of the connector.

19. The printed circuit board as defined in claim 18 , wherein each of the ground shadow vias is plated through or filled with a conductive material.

20. The printed circuit board as defined in claim 18 , wherein the ground shadow vias include ground shadow vias on opposite sides of each of the first and second signal vias.

21. The printed circuit board as defined in claim 18 , wherein the first and second signal vias and the ground shadow vias are configured to provide impedance matching.

22. The printed circuit board as defined in claim 18 , wherein the ground shadow vias are configured to provide shielding between the differential signal pairs of adjacent via patterns.

23. A method of manufacturing a printed circuit board comprising a connector footprint with at least one signal via, at least one signal via connected to a signal trace within the printed circuit board and at least one ground via connected to a ground plane within the printed circuit board, the method comprising:
drilling a first hole through the printed circuit board, the first hole passing through a pad of the signal trace;
drilling a second hole through the printed circuit board, the second hole passing through a plurality of ground planes within the printed circuit board;
from a first surface of the printed circuit board, drilling to expand a diameter of a first section of the first hole;
from a second surface, opposite the first surface, drilling to expand a diameter of a second section of the second hole;
plating the first and second holes.

24. The method of claim 23 , further comprising:
inserting a contact tail of a signal conductor of an electrical connector into the first section of the first hole.

25. The method of claim 23 , wherein:
drilling the first hole and the second hole comprise drilling with a drill of the same diameter.

Assignees

• Amphenol Corp

Inventors

• Cartier Jr Marc B

Classifications

• H05K2201/09718

  Clearance holes · CPC title

• H05K2201/09845

  Stepped hole, via, edge, bump or conductor · CPC title

• H05K1/0251

  related to vias or transitions between vias and transmission lines · CPC title

• H05K1/0253

  Impedance adaptations of transmission lines by special lay-out of power planes, e.g. providing openings (H05K1/0251 takes precedence) · CPC title

• H01R43/205 Primary

  with a panel or printed circuit board · CPC title