Printed circuit and circuit board assembly configured for quad signaling

Patent metadata

Field	Value
Publication number	US-9930772-B2
Application number	US-201514983829-A
Country	US
Kind code	B2
Filing date	Dec 30, 2015
Priority date	Dec 30, 2015
Publication date	Mar 27, 2018
Grant date	Mar 27, 2018

Abstract

Printed circuit includes a planar substrate having opposite sides and a thickness extending therebetween. The sides extend parallel to a lateral plane. The printed circuit also includes a plurality of conductive vias extending through the planar substrate in a direction that is perpendicular to the lateral plane. The conductive vias include ground vias and signal vias. The signal vias form a plurality of quad groups in which each quad group includes a two-by-two array of the signal vias. Optionally, the printed circuit also includes signal traces that electrically couple to the signal vias. The signal traces may form a plurality of quad lines in which each quad line includes four of the signal traces. The four signal traces of each quad line may extend parallel to one another and be in a two-by-two formation.

First claim

What is claimed is:

1. A printed circuit comprising:
a planar substrate having opposite sides and a thickness extending therebetween, the sides extending parallel to a lateral plane;
a plurality of conductive vias extending through the planar substrate in a direction that is perpendicular to the lateral plane, the conductive vias including ground vias and signal vias, the signal vias being arranged to form a plurality of quad groups in which each quad group includes a two-by-two arrangement of the signal vias, the ground vias being positioned between adjacent quad groups; and
a plurality of signal traces coupled to the planar substrate and extending parallel to the lateral plane;
wherein the signal traces are electrically coupled to respective signal vias of the quad groups to form a plurality of quad lines, each of the quad lines including the signal vias of a corresponding quad group and four of the signal traces, the four signal traces of each quad line extending parallel to one another and being in a two-by-two formation in which two of the signal traces are at a first depth in the planar substrate and the other two signal traces are at a second depth in the planar substrate.

2. The printed circuit of claim 1 , wherein the ground vias form shield arrays that surround respective quad groups, the signal traces of each quad line extending in the two-by-two formation outside of the corresponding shield array that surrounds the quad group of the respective quad line.

3. The printed circuit of claim 2 , wherein each quad line includes two trace pairs, each trace pair including one of the signal traces at the first depth and one of the signal traces at the second depth, the signal traces for each trace pair being vertically aligned with each other when in the two-by-two formation, wherein the two trace pairs jog away and back toward each other while being in the two-by-two formation.

4. The printed circuit of claim 2 , wherein each shield array defines a shield perimeter, the signal traces for at least one quad line breaking from the two-by-two formation within the shield perimeter.

5. The printed circuit of claim 2 , wherein the shield arrays include first, second, third, and fourth shield arrays that surround respective quad groups, the signal traces of at least one of the quad lines extending in a first direction between the first and second shield arrays and in a different second direction between the third and fourth shield arrays.

6. The printed circuit of claim 1 , wherein each quad group defines a signal perimeter, the signal traces for at least one quad line breaking from the two-by-two formation within the signal perimeter.

7. The printed circuit of claim 1 , wherein the ground vias form shield arrays that surround respective quad groups, wherein at least two of the shield arrays share at least one of the ground vias.

8. The printed circuit of claim 1 , further comprising air holes extending in the direction that is perpendicular to the lateral plane, the air holes being positioned between adjacent signal vias within a corresponding quad group, the air holes extending only partially through a thickness of the printed circuit.

9. A printed circuit comprising:
a planar substrate having opposite sides and a thickness extending therebetween, the sides extending parallel to a lateral plane; and
a quad array of conductive vias that extend through the planar substrate in a direction that is perpendicular to the lateral plane, the conductive vias including ground vias and signal vias, the signal vias forming a plurality of quad groups in which each quad group includes a two-by-two arrangement of the signal vias configured for quad signaling, the ground vias forming shield arrays that surround respective quad groups and are configured to reduce crosstalk between adjacent quad groups.

10. The printed circuit of claim 9 , wherein at least two of the shield arrays share at least one of the ground vias.

11. The printed circuit of claim 9 , wherein the quad array has rows and columns of via sub-sets, each of the via sub-sets including one quad group of the plurality of quad groups and the shield array that surrounds the one quad group.

12. The printed circuit of claim 9 , wherein at least some of the quad groups do not electrically couple to signal traces.

13. The printed circuit of claim 9 , further comprising a plurality of signal traces coupled to the planar substrate and extending parallel to the lateral plane, the signal traces being electrically coupled to respective signal vias of the quad groups to form a plurality of quad lines, each of the quad lines including the signal vias of a corresponding quad group and four of the signal traces, the four signal traces of each quad line extending parallel to one another and being in a two-by-two formation in which two of the signal traces are at a first depth in the planar substrate and the other two signal traces are at a second depth in the planar substrate.

14. The printed circuit of claim 13 , wherein the shield arrays include first, second, third, and fourth shield arrays that surround respective quad groups, the signal traces of at least one of the quad lines extending in a first direction between the first and second shield arrays and in a different second direction between the third and fourth shield arrays.

15. The printed circuit of claim 9 , further comprising air holes extending in the direction that is perpendicular to the lateral plane, the air holes being positioned between adjacent signal vias within a corresponding quad group.

16. The printed circuit of claim 15 , wherein the air holes extend only partially through a thickness of the printed circuit.

17. A circuit board assembly comprising:
an electrical connector having a connector housing and a connector array of signal and ground contacts that are coupled to the connector housing;
a circuit board having the electrical connector mounted thereto, the circuit board comprising:
a planar substrate having opposite sides and a thickness extending therebetween, the sides extending parallel to a lateral plane; and
a plurality of conductive vias extending through the planar substrate in a direction that is perpendicular to the lateral plane, the conductive vias including ground vias and signal vias, the signal vias forming a plurality of quad groups in which each quad group includes a two-by-two arrangement of the signal vias, the ground vias forming shield arrays that surround respective quad groups and are configured to reduce crosstalk between adjacent quad groups; and

wherein the signal and ground contacts of the connector array are configured to electrically and mechanically couple to the signal and ground vias, respectively, of the printed circuit.

18. The circuit board assembly of claim 17 , wherein at least two of the shield arrays share at least one of the ground vias.

19. The circuit board assembly of claim 17 , further comprising a plurality of signal traces coupled to the planar substrate and extending parallel to the lateral plane, the signal traces being electrically coupled to respective signal vias of the quad groups to form a plurality of quad lines, each of the quad lines including the signal vias of a corresponding quad group and four of the signal traces, the four signal traces of each quad line extending parallel to one another and being in a two-by-two formation in which two of the signal traces are at a first depth in the planar substrate and the other two signal traces are at a second depth in the planar substrate.

Assignees

• Tyco Electronics Corp
• Tyco Electronics Japan G K
• Te Connectivity Corp

Inventors

• Morgan Chad William
• Aizawa Masayuki
• Behziz Arash
• Costello Brian Patrick
• Tracy Nathan Lincoln
• Herring Michael David

Classifications

• H05K1/0245 Primary

  Lay-out of balanced signal pairs, e.g. differential lines or twisted lines · CPC title

• H05K2201/044

  Details of backplane or midplane for mounting orthogonal PCBs · CPC title

• H05K1/115

  Via connections; Lands around holes or via connections (H05K1/112 takes precedence) · CPC title

• H05K1/024

  Dielectric details, e.g. changing the dielectric material around a transmission line · CPC title

• H05K2201/09672

  Superposed layout, i.e. in different planes · CPC title