Backplane footprint for high speed, high density electrical connectors

Patent metadata

Field	Value
Publication number	US-10187972-B2
Application number	US-201715452096-A
Country	US
Kind code	B2
Filing date	Mar 7, 2017
Priority date	Mar 8, 2016
Publication date	Jan 22, 2019
Grant date	Jan 22, 2019

Abstract

A printed circuit board includes a plurality of layers including attachment layers and routing layers; and columns of via patterns formed in the plurality of layers, wherein via patterns in adjacent columns are offset in a direction of the columns, each of the via patterns comprising: first and second signal vias forming a differential signal pair, the first and second signal vias extending through at least the attachment layers; and at least one conductive shadow via located between the first and second signal vias of the differential pair. In some embodiments, at least one conductive shadow via is electrically connected to a conductive surface film.

First claim

What is claimed is:

1. A printed circuit board comprising:
a plurality of layers including attachment layers and routing layers; and
columns of via patterns formed in the plurality of layers, wherein via patterns in adjacent columns are offset in a direction of the columns, each of the via patterns comprising:
first and second signal vias forming a differential signal pair, the first and second signal vias extending through at least the attachment layers;
at least one conductive shadow via located between the first and second signal vias of the differential pair; and
an antipad surrounding the first and second signal vias, wherein the at least one conductive shadow via includes two or more conductive shadow vias that electrically short circuit opposite sides of the antipad between the first and second signal vias.

2. The printed circuit board as defined in claim 1 , wherein the at least one shadow via is located on a line that is perpendicular to the direction of the columns.

3. The printed circuit board as defined in claim 2 , wherein the line that is perpendicular to the direction of the columns is located midway between the first and second signal vias.

4. The printed circuit board as defined in claim 3 , wherein the two or more shadow vias are located on the line.

5. The printed circuit board as defined in claim 1 , wherein the at least one shadow via is smaller in diameter than the first and second signal vias.

6. The printed circuit board as defined in claim 1 , wherein the at least one shadow via extends through the plurality of layers.

7. The printed circuit board as defined in claim 1 , wherein the at least one shadow via is plated or filled with a conductive material.

8. The printed circuit board as defined in claim 1 , further comprising additional shadow vias located between adjacent via patterns in each of the columns.

9. The printed circuit board as defined in claim 1 , wherein each of the via patterns further comprises ground vias extending through at least the attachment layers, the ground vias including ground conductors.

10. The printed circuit board as defined in claim 9 , wherein the first and second signal vias and the ground vias are configured to accept compliant pins of a connector.

11. The printed circuit board as defined in claim 1 , wherein the antipad comprises a first antipad surrounding the first signal via and a second antipad surrounding the second signal via.

12. The printed circuit board as defined in claim 11 , wherein first and second signal traces are connected to the first and second signal vias, respectively, in a breakout layer of the routing layers and wherein the first and second antipads in a layer below the breakout layer include ground plane projections toward the first and second signal vias underneath the first and second signal traces.

Assignees

• Amphenol Corp

Inventors

• Charbonneau Marc Robert
• Paniagua Jose Ricardo

Classifications

• H05K2201/096

  Vertically aligned vias, holes or stacked vias · CPC title

• H05K2201/09845

  Stepped hole, via, edge, bump or conductor · CPC title

• H05K1/0251

  related to vias or transitions between vias and transmission lines · CPC title

• H05K2201/09727

  Varying width along a single conductor; Conductors or pads having different widths · CPC title

• H05K1/0219

  Printed shielding conductors for shielding around or between signal conductors, e.g. coplanar or coaxial printed shielding conductors · CPC title