High density ac coupling/dc blocking pin-field array

Patent metadata

Field	Value
Publication number	US-2016183373-A1
Application number	US-201414575223-A
Country	US
Kind code	A1
Filing date	Dec 18, 2014
Priority date	Dec 18, 2014
Publication date	Jun 23, 2016
Grant date	—

Abstract

Implementations of the present disclosure involve an apparatus and/or method for a large array of AC coupling/DC blocking capacitors on a printed circuit board (PCB) of a microelectronic circuit. The method provides for the placement of the blocking capacitors (and associated vias) to be placed on/through the PCB in a small area while yielding low crosstalk or interference between the vias. In one particular embodiment, the blocking capacitors are placed on the PCB in an alternating pattern, with a pair of blocking capacitors placed on the top side of the PCB followed by a pair of blocking capacitors on the bottom side of the PCB, and so on. Further, top side capacitor vias may be back-drilled from the bottom side and bottom side capacitor vias may be back-drilled from the top side.

First claim

What is claimed is:

1 . A printed circuit board (PCB) comprising:
a top surface; a bottom surface opposite the top surface; a plurality of top side signal layers, the plurality of top side signal layers in an upper half of the PCB between the top surface and the bottom surface; a plurality of bottom side signal layers, the plurality of bottom side signal layers in a lower half of the PCB between the top surface and the bottom surface; a first pair of top side blocking capacitors on the top surface, the first pair of top side blocking capacitors electrically connected to a first pair of top side vias, wherein each of the first pair of top side vias electrically connects to at least one of the plurality of top side signal layers of the PCB; a pair of bottom side blocking capacitors on the bottom surface, the pair of bottom side blocking capacitors electrically connected to a pair of bottom side vias, wherein each of the pair of bottom side vias electrically connects to at least one of the plurality of bottom side signal layers of the PCB; and a second pair of top side blocking capacitors on the top surface, the second pair of top side blocking capacitors electrically connected to a second pair of top side vias, wherein each of the second pair of top side vias electrically connects to at least one of the plurality of top side signal layers of the PCB; wherein the first pair of top side blocking capacitors, the pair of bottom side blocking capacitors, and the second pair of top side blocking capacitors are arranged on the top surface and the bottom surface in an alternating pattern.

2 . The PCB of claim 1 wherein the length of the first pair of top side vias and length of the second pair of top side vias is less than one-half the thickness of the PCB.

3 . The PCB of claim 1 wherein the length of the pair of bottom side vias is less than one-half the thickness of the PCB.

4 . The PCB of claim 2 wherein the length of the first pair of top side vias and length of the second pair of top side vias is determined by back-drilling the first pair of top side vias and the second pair of top side vias from the bottom surface of the PCB.

5 . The PCB of claim 3 wherein the length of the pair of bottom side vias is determined by back-drilling the pair of bottom side vias from the top surface of the PCB.

6 . The PCB of claim 1 further comprising a ground layer between the first pair of top side blocking capacitors and the bottom side blocking capacitors.

7 . The PCB of claim 6 further comprising a power layer between the top surface of the PCB and bottom surface of the PCB, wherein the power layer is shaped such that the power layer is not located between the first pair of top side blocking capacitors and the bottom side blocking capacitors.

8 . The PCB of claim 1 further comprising a first ground via between the first pair of top side blocking capacitors on the top surface of the PCB and a second ground via between the pair of bottom side blocking capacitors on the bottom surface of the PCB, the first ground via and the second ground via biased to a ground electrical signal.

9 . A method for fabricating a printed circuit board (PCB), the method comprising:
mounting a first pair of top side blocking capacitors on a top surface of the PCB, the first pair of top side blocking capacitors electrically connected to a first pair of top side vias, wherein each of the first pair of top side vias electrically connects to at least one of a plurality of top side signal layers, the plurality of top side signal layers in an upper half of the PCB between the top surface and a bottom surface opposite the top surface; mounting a pair of bottom side blocking capacitors on the bottom surface of the PCB, the pair of bottom side blocking capacitors electrically connected to a pair of bottom side vias, wherein each of the pair of bottom side vias electrically connects to at least one of the plurality of bottom side signal layers, the plurality of bottom side signal layers in a bottom half of the PCB between the top surface and a bottom surface; mounting a second pair of top side blocking capacitors on the top surface of the PCB, the second pair of top side blocking capacitors electrically connected to a second pair of top side vias, wherein each of the second pair of top side vias electrically connects to at least one of the plurality of top side signal layers; and wherein the first pair of top side blocking capacitors, the pair of bottom side blocking capacitors, and the second pair of top side blocking capacitors are mounted on the top surface and the bottom surface in an alternating pattern.

10 . The method of claim 9 further comprising:
back-drilling the first pair of top side vias and the second pair of top side vias from the bottom surface of the PCB.

11 . The method of claim 10 wherein the length of the first pair of top side vias and length of the second pair of top side vias resulting from the back-drilling is less than one-half the thickness of the PCB.

12 . The method of claim 9 further comprising:
back-drilling the pair of bottom side vias from the top surface of the PCB.

13 . The method of claim 12 wherein the length of the pair of bottom side vias resulting from the back-drilling is less than one-half the thickness of the PCB.

14 . The method of claim 9 further comprising:
providing a ground signal layer between the first pair of top side blocking capacitors and the bottom side blocking capacitors.

15 . The method of claim 9 further comprising:
forming a power signal layer between the top surface of the PCB and bottom surface of the PCB, wherein the signal power layer is shaped such that the power layer is isolated from between the first pair of top side blocking capacitors and the bottom side blocking capacitors.

16 . The method of claim 9 further comprising:
providing a first ground via between the first pair of top side blocking capacitors on the top surface and a second ground via between the pair of bottom side blocking capacitors on the bottom surface, the first ground via and the second ground via biased to a ground electrical signal.

17 . A computer system comprising:
a circuit fabricated on a printed circuit board (PCB), the PCB comprising:
a top surface;
a bottom surface opposite the top surface;
a plurality of top side signal layers, the plurality of top side signal layers in an upper half of the PCB between the top surface and the bottom surface;
a plurality of bottom side signal layers, the plurality of bottom side signal layers in a lower half of the PCB between the top surface and the bottom surface;
a first pair of top side blocking capacitors on the top surface, the first pair of top side blocking capacitors electrically connected to a first pair of top side vias, wherein each of the first pair of top side vias electrically connects to at least one of the plurality of top side signal layers of the PCB;
a pair of bottom side blocking capacitors on the bottom surface, the pair of bottom side blocking capacitors electrically connected to a pair of bottom side vias, wherein each of the pair of bottom side vias electrically connects to at least one of the plurality of bottom side signal layers of the PCB; and
a second pair of top side blocking capacitors on the top surface, the second pair of top side blocking capacitors electrically connected to a second pair of top side vias, wherein each of the second pair of top side vias electrically connects to at least one of the plurality of top side signal layers of the PCB;

Assignees

• Oracle Int Corp

Inventors

• Williams Ricki Dee
• Chan Ray Ping-Kwan

Classifications

• H05K2201/10015

  Non-printed capacitor · CPC title

• H05K3/0047

  Drilling of holes · CPC title

• H05K1/115

  Via connections; Lands around holes or via connections (H05K1/112 takes precedence) · CPC title

• H05K1/0298

  Multilayer circuits · CPC title

• H05K1/181 Primary

  associated with surface mounted components · CPC title