Mating backplane for high speed, high density electrical connector

Patent metadata

Field	Value
Publication number	US-10034366-B2
Application number	US-201715792953-A
Country	US
Kind code	B2
Filing date	Oct 25, 2017
Priority date	Nov 21, 2014
Publication date	Jul 24, 2018
Grant date	Jul 24, 2018

Abstract

A printed circuit board includes a plurality of layers including attachment layers and routing layers; and via patterns formed in the plurality of layers, each of the via patterns including first and second signal vias forming a differential signal pair, the first and second signal vias extending through at least the attachment layers; ground vias extending through at least the attachment layers, the ground vias including ground conductors; and shadow vias located adjacent to each of the first and second signal vias, wherein the shadow vias are free of conductive material in the attachment layers. The printed circuit board may further include slot vias extending through the attachment layers and located between via patterns.

First claim

What is claimed is:

1. A printed circuit board comprising:
a plurality of layers including attachment layers and routing layers; and
via patterns formed in one or more of the plurality of layers, each of the via patterns comprising:
first and second signal vias forming a differential signal pair, the first and second signal vias extending through the attachment layers and connecting to respective signal traces on a breakout layer of the routing layers;
ground vias extending through at least the attachment layers; and
shadow vias located adjacent to each of the signal vias and extending through the attachment layers, the shadow vias being free of conductive material in the attachment layers.

2. The printed circuit board as defined in claim 1 , wherein the shadow vias extend through the attachment layers and the routing layers.

3. The printed circuit board as defined in claim 2 , wherein the shadow vias include conductive material in the routing layers.

4. The printed circuit board as defined in claim 1 , wherein the shadow vias are located on opposite sides of the first and second signal vias.

5. The printed circuit board as defined in claim 1 , wherein the shadow vias are located on a line through the first and second signal vias.

6. The printed circuit board as defined in claim 1 , wherein ground planes of the attachment layers are removed around the first and second signal vias to form antipads.

7. The printed circuit board as defined in claim 6 , wherein the shadow vias are located at edges of the antipads.

8. The printed circuit board as defined in claim 1 , wherein the shadow vias are located on opposite sides of the first and second signal vias and wherein additional shadow vias are located on a line through the first and second signal vias.

9. The printed circuit board as defined in claim 3 , wherein the first and second signal vias are configured to accept contact tails of signal conductors of a connector and wherein the ground vias are configured to accept contact tails of ground conductors of the connector.

10. A printed circuit board comprising:
a plurality of layers including attachment layers and routing layers; and
via patterns formed in one or more of the plurality of layers, each of the via patterns comprising:
first and second signal vias forming a differential signal pair, the first and second signal vias extending through the attachment layers and connecting to respective signal traces on a breakout layer of the routing layers;
ground vias extending through at least the attachment layers; and

ground shadow vias located adjacent to each of the signal vias and extending through the attachment layers, the ground shadow vias including ground shadow conductors that interconnect ground planes of two or more of the attachment layers.

11. The printed circuit board as defined in claim 10 , wherein the ground shadow vias extend through the attachment layers and the routing layers.

12. The printed circuit board as defined in claim 10 , wherein the ground shadow vias are plated or filled with conductive material at least in the attachment layers.

13. The printed circuit board as defined in claim 10 , wherein the ground shadow vias are located on opposite sides of the first and second signal vias.

14. The printed circuit board as defined in claim 10 , wherein the ground shadow vias are located on a line through the first and second signal vias.

15. The printed circuit board as defined in claim 10 , wherein ground planes of the attachment layers are removed around the first and second signal vias to form antipads.

16. The printed circuit board as defined in claim 15 , wherein the ground shadow vias are located at edges of the antipads.

17. The printed circuit board as defined in claim 10 , wherein the ground shadow vias are located on opposite sides of the first and second signal vias and wherein additional ground shadow vias are located on a line through the first and second signal vias.

18. A printed circuit board comprising:
a plurality of layers including conductive layers separated by dielectric layers; and
via patterns formed in one or more of the plurality of layers, each of the via patterns comprising:
first and second signal vias forming a differential signal pair, the first and second signal vias extending through one or more of the plurality of layers and connecting to respective signal traces on a breakout layer of the plurality of layers;
ground vias extending through one or more of the plurality of layers; and
shadow vias located adjacent to each of the signal vias and extending through one or more of the plurality of layers.

19. The printed circuit board as defined in claim 18 , wherein the shadow vias are free of conductive material at least in the layers above the breakout layer.

20. The printed circuit board as defined in claim 18 , wherein the ground shadow vias include ground shadow conductors that interconnect ground planes of two or more of the plurality of layers.

Assignees

• Amphenol Corp

Inventors

• Gailus Mark W
• Cartier Jr Marc B
• Sivarajan Vysakh
• Levine David

Classifications

• H05K2201/097

  Alternating conductors, e.g. alternating different shaped pads, twisted pairs; Alternating components · CPC title

• H05K2201/09545

  Plated through-holes or blind vias without lands · CPC title

• H05K3/0047

  Drilling of holes · CPC title

• H05K1/0298

  Multilayer circuits · CPC title

• H05K1/0253

  Impedance adaptations of transmission lines by special lay-out of power planes, e.g. providing openings (H05K1/0251 takes precedence) · CPC title