Method of performing analog-to-digital conversion

Patent metadata

Field	Value
Publication number	US-10404264-B2
Application number	US-201816040140-A
Country	US
Kind code	B2
Filing date	Jul 19, 2018
Priority date	Sep 11, 2017
Publication date	Sep 3, 2019
Grant date	Sep 3, 2019

Abstract

A method of performing analog-to-digital conversion using a successive approximation (SAR) analog-to-digital converter (ADC). A previous digital output is compared to a range based on the first M bits of the previous digital output. If the previous digital output is within that range, a digital-to-analog converter (DAC) of the SAR ADC is preloaded with the first M bits of the previous digital output, prior to commencing bit trials. If the previous digital output is outside of that range, an offset is applied to the first M bits of the previous digital output and the DAC is preloaded based on the M bits and the offset, prior to performing bit trials. This method reduces the possibility of the next input being outside of a further range defined by the preload.

First claim

The invention claimed is:

1. A method of performing analog-to-digital conversion using a successive approximation register (SAR) analog-to-digital converter (ADC), comprising:
performing bit trials, using a digital-to-analog converter (DAC) circuit of the SAR ADC, to convert a first sample of an analog input signal into an N-bit digital output;
before performing bit trials on a second sample of the analog input signal, comparing the N-bit digital output with a first range, the first range based on the N-bit digital output;
in response to determining that the N-bit digital output is outside the first range, preloading M bits of the N-bit digital output from the first sample plus an offset onto the DAC circuit; and
performing bit trials on a second sample to determine the bits remaining.

2. The method according to claim 1 , wherein the N-bit digital output defines a second range, and the N-bit digital output is within the second range, and the first range is a subrange of the second range.

3. The method according to claim 2 , wherein the second range has a width the same as the Mth bit of the N-bit digital output.

4. The method according to claim 3 , wherein a lower bound of the second range is the value of the most significant bit (MSB) to the Mth bit of the N-bit digital output, and an upper bound is the value of the lower bound plus the value of the Mth bit.

5. The A method according to claim 4 , wherein the first range has a width the same as the Mth+1 bit of the of the N-bit digital output.

6. The method according to claim 1 , wherein the offset is half of the Mth bit.

7. The method according to claim 6 , wherein, if the N-bit digital output is greater than an upper bound of the first range, half a bit is added to the Mth bit, and if the N-bit digital output is lower than the lower bound, half a bit is subtracted from the Mth bit.

8. The method according to claim 7 , wherein the DAC comprises at least one capacitor per bit, and for the MSB to Mth bits, the DAC comprises a pair of capacitors, each having half the value of a single capacitor.

9. The method according to claim 8 , wherein a half bit is added by using one of a pair of capacitors for the Mth bit.

10. A successive approximation register (SAR) analog-to-digital converter (ADC) configured to perform bit trials to convert a first sample of an analog input signal into an N-bit digital output, the SAR ADC comprising:
a digital-to-analog converter (DAC) circuit; and
a control circuit configured to:
compare the N-bit digital output with a first range, the first range based on the N-bit digital output, before performing bit trials on a second sample of the analog input signal;
in response to determining that the N-bit digital output is outside the first range, instruct the DAC to preload M bits of the N-bit digital output from the first sample plus an offset onto the DAC circuit; and
instruct the DAC to perform bit trials on a second sample to determine the bits remaining.

11. The SAR ADC according to claim 10 , wherein the DAC comprises:
an array of binary-weighted capacitors, wherein one or more of the binary-weighted capacitors corresponds to each bit of the DAC.

12. The SAR ADC according to claim 11 , wherein one or more of the bits of the DAC have a corresponding pair of binary-weighted capacitors in the array, and each of the pair of capacitors is configured to produce an analog output equivalent to half a bit.

13. The SAR ADC according to claim 12 , wherein each pair of binary-weighted capacitors in the array are further configured to generate an analog output equivalent to the corresponding bit of the DAC.

14. The SAR ADC according to claim 12 , wherein the half-bit value is achieved by charging one of the capacitors, and the full-bit value is achieved by charging both capacitors.

15. The SAR ADC according to claim 10 , wherein the offset is half the Mth bit.

16. The SAR ADC according to claim 10 , wherein the Mth bit is counted from the most significant bit (MSB).

17. A method of preloading a digital-to-analog converter (DAC) arranged to perform bit trials in an analog-to-digital converter (ADC), comprising:
determining a subrange defined by the first M bits of the previous N-bit digital output of the ADC, the subrange having a central portion and edge portions;
determining the position of the previous digital output within the subrange; and
in response that to determining that the previous digital output is within the edge portions, preloading the M bits plus an offset onto the DAC.

18. The method according to claim 17 , wherein the offset is a half-bit.

19. The method according to claim 17 , wherein the central portion is the middle two quarters of the range, and the edge portions and the outer two quarters of the subrange.

20. The method according to claim 17 , wherein in response to determining that the previous digital output is in an upper edge portion, a positive offset is added to the preload, and in response to determining that the previous digital output is in a lower edge portion, a negative offset is added to the preload.

21. The method according to claim 1 , further comprising:
in response to determining that the N-bit digital output is within the first range, preloading M bits of the N-bit digital output from the first sample onto the DAC circuit.

22. The SAR ADC according to claim 10 , wherein the control circuit is configured to:
in response to determining that the N-bit digital output is within the first range, instruct the DAC to preload M bits of the N-bit digital output from the first sample onto the DAC circuit.

23. The method according to claim 17 , further comprising:
in response to determining that the previous digital output is within the central portion of the subrange, preloading the M bits onto the DAC.

Assignees

• Analog Devices Inc

Inventors

• Chen Baozhen
• Fernando Lalinda D
• Tan Zhichao

Classifications

• H03M1/462 Primary

  Details of the control circuitry, e.g. of the successive approximation register · CPC title

• H03M1/002

  Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed · CPC title

• H03M1/468 Primary

  in which the input S/H circuit is merged with the feedback DAC array · CPC title