Adding predefined offset to coarse ADC residue output to SAR

Patent metadata

Field	Value
Publication number	US-9148166-B2
Application number	US-201414255269-A
Country	US
Kind code	B2
Filing date	Apr 17, 2014
Priority date	Dec 31, 2013
Publication date	Sep 29, 2015
Grant date	Sep 29, 2015

Abstract

A successive approximation register analog to digital converter (SAR ADC) receives an input voltage and a plurality of reference voltages. The SAR ADC includes a charge sharing DAC. The charge sharing DAC includes an array of MSB (most significant bit) capacitors and an array of LSB (least significant bit) capacitors. A zero crossing detector is coupled to the charge sharing DAC. The zero crossing detector generates a digital output. A coarse ADC (analog to digital converter) receives the input voltage and generates a coarse output. A predefined offset is added to a residue of the coarse ADC. A successive approximation register (SAR) state machine is coupled to the coarse ADC and the zero crossing detector and, generates a plurality of control signals. The plurality of control signals operates the charge sharing DAC in a sampling mode, an error-correction mode and a conversion mode.

First claim

What is claimed is:

1. A successive approximation register analog to digital converter (SAR ADC), configured to receive an input voltage and a set of reference voltages, comprising:
a charge sharing DAC comprising an array of MSB (most significant bit) capacitors and an array of LSB (least significant bit) capacitors;
a zero crossing detector coupled to the charge sharing DAC, the zero crossing detector configured to generate a digital output;
a coarse ADC (analog to digital c…

Assignees

• Texas Instruments Inc

Inventors

• Narayan Subramanian Jagdish
• Kannan Anand

Classifications

• H03M1/468

  Electricity · mapped topic

• H03M1/0695

  Electricity · mapped topic

• H03M1/0604 Primary

  Electricity · mapped topic

• H03M1/144

  Electricity · mapped topic

• H03M1/06

  Electricity · mapped topic