Predictive successive approximation register analog-to-digital conversion device and method

Patent metadata

Field	Value
Publication number	US-8963761-B2
Application number	US-201313954631-A
Country	US
Kind code	B2
Filing date	Jul 30, 2013
Priority date	Aug 3, 2012
Publication date	Feb 24, 2015
Grant date	Feb 24, 2015

Abstract

A predictive successive approximation register analog-to-digital conversion device and method are provided. A difference between two input signals of a comparator is detected according to a threshold less than or equal to ½ of a voltage increment represented by one least significant bit (LSB). When a difference between a first analog signal and a second analog signal is less than a threshold, a detection circuit enables a bit in a digital signal corresponding to a comparison cycle to which the difference belongs to be forcedly decided to be a first value and predicts values of the remaining bits.

First claim

What is claimed is:

1. A predictive successive approximation register (SAR) analog-to-digital conversion device, comprising:
a SAR analog-to-digital converter (ADC), comprising:
a first comparator, having a first input end for receiving a first analog signal, a second input end for receiving a second analog signal, and an output end;
a digital-to-analog converter (DAC), connected electrically to the second input end of the first comparator; and
a SAR control circuit, coupled to a control end of the DAC and the output end of the first comparator, for controlling an output of the DAC using a SAR algorithm, and generating a digital signal according to a comparison result of the first comparator; and

a detection circuit, for when a difference between the first analog signal and the second analog signal is less than a threshold, enabling a bit of the digital signal corresponding to a comparison cycle to which the difference belongs to be forcedly decided to be a first value.

2. The predictive SAR analog-to-digital conversion device according to claim 1 , wherein the threshold is less than or equal to half of a voltage increment represented by one least significant bit (LSB).

3. The predictive SAR analog-to-digital conversion device according to claim 1 , wherein when the difference is less than the threshold, the detection circuit enables each bit in the digital signal lower than the bit corresponding to the comparison cycle to which the difference belongs to be forcedly decided to be a second value.

4. The predictive SAR analog-to-digital conversion device according to claim 1 , wherein the detection circuit is coupled to the SAR control circuit, and when the difference is less than the threshold, the detection circuit enables the SAR control circuit to stop a subsequent comparison operation.

5. The predictive SAR analog-to-digital conversion device according to claim 1 , wherein the detection circuit comprises:
an addition circuit, having a first input end for receiving the digital signal and a second input end;
a compensation circuit, coupled to the second input end of the addition circuit, for outputting a corresponding compensation signal to the addition circuit in each comparison cycle according to a lookup table recording a plurality of compensation signals corresponding to a plurality of comparison cycles respectively; and
a detection unit, for actuating the addition circuit to add the digital signal and the compensation signal to generate a digital output signal when the difference is less than the threshold, wherein the bit in the digital signal corresponding to the comparison cycle to which the difference belongs is the first value.

6. The predictive SAR analog-to-digital conversion device according to claim 1 , wherein the detection circuit comprises:
a second comparator, an input end of the second comparator coupled to the output end of the first comparator, for detecting a meta-stable state of an output of the first comparator, wherein when the meta-stable state is detected, the difference is less than the threshold.

7. The predictive SAR analog-to-digital conversion device according to claim 1 , wherein the detection circuit comprises:
a second comparator, a first differential input end of the second comparator connected electrically to the first input end and the second input end of the first comparator, a second differential input end of the second comparator for receiving the threshold.

8. A predictive successive approximation register (SAR) analog-to-digital conversion device, comprising:
a SAR analog-to-digital converter (ADC), comprising:
an amplifier, for amplifying a first analog signal and a second analog signal by the same amplification factor,
a first comparator, having a first input end for receiving an amplified first analog signal, a second input end for receiving an amplified second analog signal, and an output end;
a digital-to-analog converter (DAC), connected electrically to the second input end of the first comparator; and
a SAR control circuit, coupled to a control end of the DAC and the output end of the first comparator, for controlling an output of the DAC using a SAR algorithm, and generating a digital signal according to a comparison result of the first comparator; and

a detection circuit, for when a difference between the amplified first analog signal and the amplified second analog signal is less than a threshold amplified by an amplification factor, enabling a bit in the digital signal corresponding to a comparison cycle to which the difference belongs to be forcedly decided to be a first value.

9. The predictive SAR analog-to-digital conversion device according to claim 8 , wherein the threshold is less than or equal to half of a voltage increment represented by one least significant bit (LSB).

10. The predictive SAR analog-to-digital conversion device according to claim 8 , wherein when the difference is less than the threshold amplified by the amplification factor, the detection circuit enables bits in the digital signal lower than the bit corresponding to the comparison cycle to which the difference belongs to be forcedly decided to be a second value.

11. The predictive SAR analog-to-digital conversion device according to claim 8 , wherein the detection circuit comprises:
an addition circuit, having a first input end for receiving the digital signal and a second input end;
a compensation circuit, coupled to the second input end of the addition circuit, for outputting a corresponding compensation signal to the addition circuit in each comparison cycle according to a lookup table recording a plurality of compensation signals corresponding to a plurality of comparison cycles respectively; and
a detection unit, for actuating the addition circuit to add the digital signal and the compensation signal to generate a digital output signal when the difference is less than the threshold amplified by the amplification factor, wherein the bit of the digital signal corresponding to the comparison cycle to which the difference belongs is the first value.

12. The predictive SAR analog-to-digital conversion device according to claim 8 , wherein the detection circuit comprises:
a second comparator, an input end of the second comparator coupled to the output end of the first comparator, for detecting a meta-stable state of an output of the first comparator, wherein when the meta-stable state is detected, the difference is less than the threshold amplified by the amplification factor.

13. The predictive SAR analog-to-digital conversion device according to claim 8 , wherein the detection circuit comprises:
a second comparator, a first differential input end of the second comparator connected electrically to the first input end and the second input end of the first comparator, a second differential input end of the second comparator for receiving the threshold amplified by the amplification factor.

14. A predictive successive approximation register (SAR) analog-to-digital conversion method, comprising:
comparing a first analog signal with a second analog signal in each of a plurality of comparison cycles by a comparator;
providing the corresponding second analog signal using a SAR algorithm in each comparison cycle;
generating a digital signal according to a comparison result of the comparator;
detecting a difference between the first analog signal and the second analog signal according to a threshold in each comparison cycle; and
when the difference is less than the threshold, forcedly deciding a bit in the digital signal corresponding to a comparison cycle to which the difference belongs

Assignees

• Realtek Semiconductor Corp

Inventors

• Tsai Jen-Huan
• Huang Po-Chiun
• Huang Shih-Hsiun

Classifications

• H03M1/12 Primary

  Analogue/digital converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

• H03M1/466 Primary

  using switched capacitors · CPC title