Successive-approximation-register (SAR) analog-to-digital converter (ADC) attenuation capacitor calibration method and apparatus

Patent metadata

Field	Value
Publication number	US-8981973-B2
Application number	US-201414197951-A
Country	US
Kind code	B2
Filing date	Mar 5, 2014
Priority date	Mar 8, 2013
Publication date	Mar 17, 2015
Grant date	Mar 17, 2015

Abstract

A fixed capacitor is coupled between a top plate of an attenuation capacitor and a variable voltage reference. The error in the attenuation capacitor may be calibrated out with the variable voltage reference and the fixed correction capacitor. The variable voltage reference varies the charge on the attenuation capacitor and thereby compensates for error(s) therein. A calibration digital-to-analog converter may be used in conjunction with or substituted for the variable voltage reference, and may be programmed for different charge compensation values from the SAR logic during an iterative SAR DAC capacitive switching process.

First claim

What is claimed is:

1. An apparatus for calibrating a successive-approximation register (SAR) analog-to-digital converter (ADC), comprising:
a most significant bit digital-to-analog converter (mDAC) comprising a plurality of binary weighted first capacitors;
a lower bit digital-to-analog converter (nDAC) comprising a plurality of binary weighted second capacitors;
an attenuation capacitor coupled between the mDAC and the nDAC;
a correction capacitor having a fixed capacitance value, wherein the correction capacitor is coupled to the attenuation capacitor; and
a variable voltage reference is coupled to the fixed value capacitor;
wherein a voltage from the variable voltage reference is adjusted to vary a charge on the correction capacitor for compensating a capacitance value error of the attenuation capacitor.

2. The apparatus according to claim 1 , wherein a first plate of the correction capacitor is coupled to the attenuation capacitor and a second plate of the correction capacitor is coupled to the variable voltage reference.

3. The apparatus according to claim 1 , wherein the correction capacitor and the plurality of binary weighted second capacitors are fixed value metal-insulator-metal (MIM) capacitors.

4. The apparatus according to claim 1 , wherein the correction capacitor and the plurality of binary weighted second capacitors are fixed value metal-oxide-metal (MOM) capacitors.

5. The apparatus according to claim 1 , wherein adjustment of the variable voltage reference is programmable.

6. The apparatus according to claim 5 , wherein the programmable variable voltage reference is programmed from a successive approximation register (SAR).

7. The apparatus according to claim 6 , wherein the SAR controls which of the plurality of binary weighted first and second capacitors are selected during an analog-to-digital conversion by the SAR DAC.

8. The apparatus according to claim 5 , wherein the programmable variable voltage reference is programmed from the SAR for a plurality of different charges on the correction capacitor to compensate for a plurality of different capacitance value errors of the attenuation capacitor.

9. The apparatus according to claim 8 , wherein which one of the plurality of different charges on the correction capacitor is programmed depends upon which ones of the plurality of binary weighted first and second capacitors are selected by the SAR.

10. An apparatus for calibrating a successive-approximation register (SAR) analog-to-digital converter (DAC), comprising:
a most significant bit digital-to-analog converter (mDAC) comprising a plurality of binary weighted first capacitors;
a lower bit digital-to-analog converter (nDAC) comprising a plurality of binary weighted second capacitors;
an attenuation capacitor coupled between the mDAC and the nDAC;
a correction capacitor having a fixed capacitance value, wherein the correction capacitor is coupled to the attenuation capacitor; and
a calibration digital-to-analog converter (cDAC) coupled to the fixed value capacitor;
wherein a voltage from the cDAC is programmed to vary a charge on the correction capacitor for compensating a capacitance value error of the attenuation capacitor.

11. The apparatus according to claim 10 , wherein a first plate of the correction capacitor is coupled to the attenuation capacitor and a second plate of the correction capacitor is coupled to the cDAC.

12. The apparatus according to claim 10 , wherein the correction capacitor and the plurality of binary weighted second capacitors are fixed value metal-insulator-metal (MIM) capacitors.

13. The apparatus according to claim 10 , wherein the correction capacitor and the plurality of binary weighted second capacitors are fixed value metal-oxide-metal (MOM) capacitors.

14. The apparatus according to claim 10 , wherein the cDAC is programmed from a successive approximation register (SAR).

15. The apparatus according to claim 14 , wherein the SAR controls which of the plurality of binary weighted first and second capacitors are selected during an analog-to-digital conversion by the SAR DAC.

16. The apparatus according to claim 14 , further comprising a voltage reference coupled to the cDAC.

17. The apparatus according to claim 16 , wherein the voltage reference is programmable.

18. The apparatus according to claim 17 , wherein the programmable variable voltage reference is programmed from the SAR.

19. The apparatus according to claim 18 , wherein the programmable variable voltage reference is programmed from the SAR for a plurality of different charges on the correction capacitor.

20. The apparatus according to claim 19 , wherein which one of the plurality of different charges on the correction capacitor is programmed depends upon which ones of the plurality of binary weighted first and second capacitors are selected by the SAR.

21. A method for calibrating a successive-approximation register (SAR) analog-to-digital converter (DAC), said method comprising the steps of:
providing a most significant bit digital-to-analog converter (mDAC) comprising a plurality of binary weighted first capacitors;
providing a lower bit digital-to-analog converter (nDAC) comprising a plurality of binary weighted second capacitors;
providing an attenuation capacitor coupled between the mDAC and the nDAC;
providing a correction capacitor having a fixed capacitance value, wherein the correction capacitor is coupled to the attenuation capacitor; and
varying a voltage on the correction capacitor to compensate for a capacitance value error of the attenuation capacitor.

22. The method according to claim 21 , wherein the variable voltage is from a variable voltage reference.

23. The method according to claim 21 , wherein the variable voltage is from a calibration digital-to-analog converter (cDAC).

Assignees

• Microchip Tech Inc

Inventors

• Kumar Ajay

Classifications

• H03M1/468

  in which the input S/H circuit is merged with the feedback DAC array · CPC title

• H03M1/804

  with charge redistribution · CPC title

• H03M1/68

  with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits · CPC title

• H03M1/0617 Primary

  characterised by the use of methods or means not specific to a particular type of detrimental influence · CPC title

• H03M1/1061 Primary

  using digitally programmable trimming circuits · CPC title