Sensory array with non-correlated double sampling random access-reset pixel and multi-channel readout

Patent metadata

Field	Value
Publication number	US-9467638-B2
Application number	US-201414459187-A
Country	US
Kind code	B2
Filing date	Aug 13, 2014
Priority date	Aug 13, 2013
Publication date	Oct 11, 2016
Grant date	Oct 11, 2016

Abstract

Integration of high-fidelity readout and compressive readout channels in a signal sensor array system is provided. A high-fidelity representation of the sensor array is recovered by combining the data from both the high-resolution and compressive readout channels. The signal sensory array system uses a non-correlated-double-sampling (non-CDS) pixel block readout, random-access-reset pixel, ADC-integrated image compression, high-resolution successive-approximation-register (SAR) analog-to-digital-converters (ADC), SAR ADC self-calibration, and low-noise time-domain comparator.

First claim

What is claimed is:

1. A system, comprising:
a first readout channel comprising a first quantization resolution level analog-to-digital converter and a first quantization resolution level multiplexer, wherein a first performance metric of the first readout channel satisfies a threshold level;
a second readout channel comprising a second quantization resolution level analog-to-digital converter and a second quantization resolution level multiplexer, wherein a second performance metric of the second readout channel does not satisfy the threshold level; and
a sensory array comprising a first set of sensors associated with the first readout channel and a second set of sensors associated with the second readout channel.

2. The system of claim 1 , wherein a sensor of the sensory array comprises a P+-implant-N-substrate photo-diode comprising a buried N-type metal-oxide-semiconductor reset transistor.

3. The system of claim 1 , wherein a sensor of the sensory array comprises a N+-implant-P-substrate photo-diode comprising a buried P-type metal-oxide-semiconductor reset transistor.

4. The system of claim 1 , wherein a sensor of the sensory array comprises:
an in-well reset transistor comprising a parasitic diode; and
a delay element, connected to a reset signal of the sensor, configured to charge a bias voltage of the parasitic diode of the in-well reset transistor to prevent the bias voltage from becoming forward biased after a pixel reset process.

5. The system of claim 1 , wherein a sensor of the sensory array comprises an in-pixel logic circuit comprising:
a set of select transistors each configured to receive one or more reset signals, wherein the sensor is configured to alter, based on the one or more reset signals, a state associated with the sensor.

6. The system of claim 1 , wherein the first readout channel comprises at least one high-resolution readout channel that is multiplexed onto the first set of sensors, and wherein the at least one high-resolution readout channel comprises at least one multiplexer and at least one high-resolution analog-to-digital converter.

7. The system of claim 6 , wherein the at least one high-resolution analog-to-digital converter comprises an analog multiplexer configured to select, in response to receiving a series of reference signals, at least one least-significant-bit.

8. The system of claim 6 , wherein the at least one high-resolution readout channel further comprises:
a comparator configured to compare a reference voltage signal, received at a first input of the comparator, with a feedback signal received at a second input of the comparator;
a pilot digital-to-analog converter, coupled to the comparator, configured to provide the feedback signal to the second input of the comparator and update the feedback signal; and
a register, coupled to the pilot digital-to-analog converter, configured to store bits of data that represent an output of the comparator.

9. The system of claim 8 , wherein the pilot digital-to-analog converter comprises a binary weighting device configured to apply a binary weighted sizing to a buffer of a reference signal, and wherein the binary weighting device further comprises an error correction weight device.

10. The system of claim 8 , wherein the pilot digital-to-analog converter further comprises a set of weight devices arranged as at least two scaled segments and configured to facilitate a forward error correction process.

11. The system of claim 8 , wherein the at least one high-resolution readout channel is further configured to determine, based on two references and a pre-biased offset of a most-significant-bit evaluation process, a bipolar error correction range.

12. The system of claim 8 , wherein the pilot digital-to-analog converter is further configured to perform mixed signal corrective double sampling based on pre-loading the pilot digital-to-analog converter with a pre-load value during a sampling process.

13. The system of claim 8 , wherein the pilot digital-to-analog converter comprises a set of weighting devices that are hierarchically nested and wherein most-significant-bit estimations are made consecutively from a lowest hierarchical level to a highest hierarchical level with bipolar error correction phases inserted in each transition from respective lower levels to respective higher levels.

14. The system of claim 8 , wherein the pilot digital-to-analog converter further comprises a set of weight devices, and a shielding metal layer drawn proportionally to respective sizes of the set of weight devices of the set of weight devices.

15. The system of claim 6 , wherein the at least one high-resolution analog-to-digital converter is further configured to perform a self-calibration process based on a register mask, wherein the self-calibration process comprises:
connecting bottom plates of capacitors of the at least one high-resolution analog-to-digital converter to the register mask; and
in response to a sampling process, restoring the bottom plates of the capacitors of the at least one high-resolution analog-to-digital converter to a constant signal and settling charge-redistribution of a voltage associated with the capacitors as a function of a weight indicated by the register mask.

16. The system of claim 6 , wherein the at least one high-resolution analog-to-digital converter comprises:
a comparator comprising at least one voltage controlled delay component and an arbiter, wherein the at least one voltage controlled delay component comprises a set of delay stage devices that receive a clock signal and a set of biased devices, and wherein the set of biased devices are configured to be smaller than the at least one voltage controlled delay component and to facilitate a delay stage by controlling a current supplied to the at least one voltage controlled delay component.

17. A method, comprising:
selecting, by a system comprising a processor, a set of high-resolution pixels from a pixel array;
receiving, by a high-quantization resolution channel comprising a high-resolution multiplexer and a high-resolution analog-to-digital converter, data associated with the set of high-resolution pixels;
selecting, by the system, a set of low-resolution pixels from the pixel array, wherein the high-resolution is higher than the low-resolution; and
receiving, by a low-quantization resolution channel comprising a low resolution multiplexer and a low-resolution analog-to-digital converter, data associated with the set of low-resolution pixels, wherein the high-quantization resolution channel and the low-quantization resolution channel are configured for satisfaction of different performance metrics.

18. The method of claim 17 , further comprising:
in response to receiving the data associated with the set of low-resolution pixels, altering the set of high-resolution pixels by reselecting the set of high-resolution pixels from the pixel array based on a region of interest determined based on the data associated with the set of low-resolution pixels; and
in response to receiving the data associated with the set of high-resolution pixels, altering the set of low-resolution pixels by reselecting the set of low-resolution pixels from the pixel array based on the region of interest determined based on the data associated with the set of high-resolution pixels.

19. The method of claim 17 , further comprising:
applying a constant signal to bottom plates of capacitors, excluding a most-significant-bit capacitor, of a negative digital-to-analog converter of a high-resolut

Assignees

• Univ Hong Kong Science & Tech

Inventors

• Chen Denis Guangyin
• Bermak Amine

Classifications

• H04N25/767 Primary

  Horizontal readout lines, multiplexers or registers · CPC title

• H04N25/78

  Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters · CPC title

• H04N5/3742

  Electricity · mapped topic

• H04N5/378 Primary

  Electricity · mapped topic

• H04N25/00

  Circuitry of solid-state image sensors [SSIS]; Control thereof · CPC title