Time-interleaved analog to digital converter based on control of counter
US-2024113726-A1 · Apr 4, 2024 · US
Hybrid analog-to-digital converter having multiple ADC modes
US8933385B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8933385-B2 |
| Application number | US-201213543470-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jul 6, 2012 |
| Priority date | Jul 6, 2012 |
| Publication date | Jan 13, 2015 |
| Grant date | Jan 13, 2015 |
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Abstract
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A hybrid ADC having a successive approximation register (SAR) ADC mode for generating a bit of a digital signal and a ramp ADC mode for generating an additional bit of the digital signal is disclosed. When in the SAR ADC mode, a control circuit is configured to disable a ramp signal generator; disable a counter; and enable a register to control an offset stage to set the magnitude of an offset voltage that is provided to an input of a comparator of the ADC. When in the ramp ADC mode, the control circuit is configured to enable the ramp signal generator to provide a ramp signal to the input of the comparator; enable the counter to begin providing the digital count in response to the output of the comparator; and disable the register so that the offset stage is not providing the offset voltage.
First claim
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What is claimed is: 1. A hybrid analog to digital converter (ADC) having a successive approximation register (SAR) ADC mode for generating at least one bit of a digital signal and a ramp ADC mode for generating at least one additional bit of the digital signal, the hybrid ADC comprising: a sampling stage coupled to receive and sample an analog input; a comparator having a first input coupled to receive an output of the sampling stage and a second input coupled to receive a first…
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- What does patent US8933385B2 cover?
- A hybrid ADC having a successive approximation register (SAR) ADC mode for generating a bit of a digital signal and a ramp ADC mode for generating an additional bit of the digital signal is disclosed. When in the SAR ADC mode, a control circuit is configured to disable a ramp signal generator; disable a counter; and enable a register to control an offset stage to set the magnitude of an offset …
- Who is the assignee on this patent?
- Wang Rui, Deng Liping, Dai Tiejun, and 1 more
- What technology area does this patent fall under?
- Primary CPC classification H03M1/145. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Jan 13 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).