Incremental preloading in an analog-to-digital converter

Patent metadata

Field	Value
Publication number	US-9712181-B1
Application number	US-201615273967-A
Country	US
Kind code	B1
Filing date	Sep 23, 2016
Priority date	Sep 23, 2016
Publication date	Jul 18, 2017
Grant date	Jul 18, 2017

Abstract

During operation of a SAR ADC, several of the MSBs can be preloaded with predetermined bit decisions prior to carrying out bit trials. A system and method can be provided for incrementally preloading the predetermined bit decisions such as to maintain voltages present at comparator inputs within a limited range of acceptable input voltages.

First claim

The invention claimed is:

1. A method of loading at least one bit decision onto a charge redistribution digital-to-analog converter (DAC) including an array of capacitive elements corresponding to different bit positions, the method comprising:
partially loading onto a first element having a first bit position, a charge associated with a first bit decision of the first element having the first bit position;
at least partially loading onto a second element having a second bit position that is different from the first bit position, a charge associated with a second bit decision of the second element having the second bit position; and
then further loading onto the first element having the first bit position, further charge associated with the first bit decision of the first element.

2. The method of claim 1 , wherein:
the partially loading onto the first element having the first bit position comprises, applying a voltage associated with the first bit decision of the first element having the first bit position onto a capacitor segment that is less than an entire aggregate capacitor associated with the first element having the first bit position.

3. The method of claim 2 , comprising determining a relationship between charge associated with the first bit decision and charge associated with the second bit decision and based on the determined relationship, incrementally performing the loading of charge onto the first element and the second element.

4. The method of claim 2 , comprising predetermining the first bit decision and the second bit decision using a separate auxiliary ADC.

5. The method of claim 2 , wherein the first element and the second element respectively correspond to the most significant bit and the next most significant bit of the DAC.

6. The method of claim 2 , wherein the partially loading onto the first element having a first bit position and the at least partially loading onto the second element having a second bit position are performed concurrently.

7. The method of claim 6 , comprising then further loading onto the first element having the first bit position, further charge associated with the first bit decision of the first element and further loading onto the second element having the second bit position, further charge associated with the second bit decision of the second element, wherein the further loading onto the first element and the further loading onto the second element are performed concurrently.

8. The method of claim 2 , wherein the partially loading onto the first element having a first bit position and the at least partially loading onto the second element having a second bit position are performed sequentially.

9. A system for loading at least one bit decision onto a charge redistribution digital-to-analog (DAC) converter having an array of capacitive elements, the system comprising:
a first element having a first bit position;
a second element having a second bit position that is different from the first bit position; and
control circuitry configured to (i) partially load onto the first element having a first bit position, a charge associated with a first bit decision of the first element having the first bit position (ii) at least partially loading onto the second element having a second bit position, a charge associated with a second bit decision of the second element having the second bit position, and (iii) then further load onto the first element having the first bit position, further charge associated with the first bit decision of the first element.

10. The system of claim 9 , wherein the first element having the first bit decision includes multiple capacitor segments and the control circuitry is further configured to apply a voltage associated with the first bit decision of the first element having the first bit position onto at least one capacitor segment, but not all of the multiple capacitor segments of the first element.

11. The system of claim 10 , wherein the control circuitry is further configured to determine a relationship between charge associated with the first bit decision and charge associated with the second bit decision and based on the determined relationship, incrementally perform the loading of charge onto the first element and the second element.

12. The system of claim 10 , comprising a separate auxiliary ADC configured to predetermine the first bit decision and the second bit decision.

13. The system of claim 10 , wherein the first element and the second element respectively correspond to the most significant bit and the next most significant bit of the DAC.

14. The system of claim 10 , wherein the controller is further configured to load charge onto the first element and the second element concurrently.

15. The system of claim 14 , wherein the controller is further configured to then further load onto the first element having the first bit position, further charge associated with the first bit decision of the first element and simultaneously further load onto the second element having the second bit position, further charge associated with the second bit decision of the second element.

16. The system of claim 10 , wherein the controller is further configured to load charge onto the first element and the second element sequentially.

17. A method of loading at least one bit decision onto a charge redistribution digital-to-analog converter (DAC) including a thermometer encoded array including a sequence of logically adjacent capacitive cells corresponding to different bit positions, the method comprising:
loading onto a first cell having a position in the array of capacitive cells determined by a logical midpoint of the thermometer encoded array, a charge associated with a decoded most significant bit (MSB) decision; and
then partially loading onto a second cell logically adjacent to the first cell, a charge associated with a decoded second bit decision, and partially loading onto a third element logically adjacent to the first cell, a charge associated with a decoded third bit decision and then further loading onto the second cell logically adjacent to the first cell, a charge associated with a decoded second bit decision.

18. The method of claim 17 wherein the decoded MSB decision is a majority bit decision included with a majority of the capacitive cells sharing a like charge in the sequence of logically adjacent capacitive cells.

19. The method of claim 18 wherein the second bit decision is a majority bit decision included with a majority of the capacitive cells sharing a like charge in the sequence of logically adjacent capacitive cells, and the third hit decision is a minority bit decision included with a minority of the capacitive cells sharing a like charge in the sequence of adjacent capacitive cells.

20. The method of claim 18 wherein the second bit decision is a majority bit decision included with a majority of the capacitive cells sharing a like charge in the sequence of logically adjacent capacitive cells, and the third bit decision is a majority bit decision included with a majority of the capacitive cells sharing a like charge in the sequence of adjacent capacitive cells.

Assignees

• Analog Devices Inc

Inventors

• Chen Baozhen
• Guthrie Edward C
• Coln Michael C W
• Maddox Mark D

Classifications

• H03M1/466 Primary

  using switched capacitors · CPC title

• H03M1/1245 Primary

  Details of sampling arrangements or methods · CPC title

• H03M1/806

  with equally weighted capacitors which are switched by unary decoded digital signals · CPC title

• H03M1/68

  with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits · CPC title

• H03M1/14

  Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit · CPC title