Method for making CMOS image sensor with buried superlattice layer to reduce crosstalk

Patent metadata

Field	Value
Publication number	US-10396223-B2
Application number	US-201715843044-A
Country	US
Kind code	B2
Filing date	Dec 15, 2017
Priority date	Dec 15, 2017
Publication date	Aug 27, 2019
Grant date	Aug 27, 2019

Abstract

A method for making a CMOS image sensor may include forming a superlattice on a semiconductor substrate having a first conductivity type, with the superlattice including a plurality of stacked groups of layers. Each group of layers may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and a non-semiconductor monolayer(s) constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming a plurality of laterally adjacent photodiodes on the superlattice. Each photodiode may include a semiconductor layer on the superlattice and having a first conductivity type dopant and with a lower dopant concentration than the semiconductor substrate, a retrograde well extending downward into the semiconductor layer and having a second conductivity type, a first well around a periphery of the retrograde well having the first conductivity type, and a second well within the retrograde well having the first conductivity type.

First claim

That which is claimed is:

1. A method for making a CMOS image sensor comprising:
forming a superlattice on a semiconductor substrate having a first conductivity type, the superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions; and
forming a plurality of laterally adjacent photodiodes on the superlattice by
forming a semiconductor layer on the superlattice and having a first conductivity type dopant and with a lower dopant concentration than the semiconductor substrate,
forming a retrograde well extending downward into the semiconductor layer from a surface thereof and having a second conductivity type,
forming a first well around a periphery of the retrograde well having the first conductivity type, and
forming a second well overlying the retrograde well having the first conductivity type.

2. The method of claim 1 wherein the first well defines a ring, and wherein the second well is within the ring.

3. The method of claim 1 further comprising forming a respective microlens overlying each of the photodiodes.

4. The method of claim 1 further comprising forming a respective color filter overlying each of the photodiodes.

5. The method of claim 1 further comprising forming a respective shallow trench isolation (STI) region between pairs of laterally adjacent photodiodes.

6. The method of claim 1 further comprising forming an oxide layer overlying the second well.

7. The method of claim 1 wherein the superlattice further comprises a semiconductor cap layer thereon.

8. The method of claim 1 wherein the at least one non-semiconductor monolayer comprises oxygen.

9. The method of claim 1 wherein the semiconductor monolayers comprise silicon.

10. A method for making a CMOS image sensor comprising:
forming a superlattice on a semiconductor substrate having a first conductivity type, the superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions;
forming a plurality of laterally adjacent photodiodes on the superlattice by
forming a semiconductor layer on the superlattice and having a first conductivity type dopant and with a lower dopant concentration than the semiconductor substrate,
forming a retrograde well extending downward into the semiconductor layer from a surface thereof and having a second conductivity type,
forming a first well around a periphery of the retrograde well having the first conductivity type, and
forming a second well overlying the retrograde well having the first conductivity type;

forming a respective color filter overlying each of the photodiodes; and
forming a respective microlens overlying each of the color filters.

11. The method of claim 10 wherein the first well defines a ring, and wherein the second well is within the ring.

12. The method of claim 10 further comprising forming a respective shallow trench isolation (STI) region between pairs of laterally adjacent photodiodes.

13. The method of claim 10 further comprising forming an oxide layer overlying the second well.

14. A method for making a CMOS image sensor comprising:
forming a superlattice on a semiconductor substrate having a first conductivity type, the superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base silicon monolayers defining a base silicon portion, and at least one oxygen monolayer constrained within a crystal lattice of adjacent base oxygen portions; and
forming a plurality of laterally adjacent photodiodes on the superlattice by
forming a semiconductor layer on the superlattice and having a first conductivity type dopant and with a lower dopant concentration than the semiconductor substrate,
forming a retrograde well extending downward into the semiconductor layer from a surface thereof and having a second conductivity type,
forming a first well around a periphery of the retrograde well having the first conductivity type, and
forming a second well within the retrograde well having the first conductivity type.

15. The method of claim 14 wherein the first well defines a ring, and wherein the second well is within the ring.

16. The method of claim 14 further comprising forming a respective microlens overlying each of the photodiodes.

17. The method of claim 14 further comprising forming a respective color filter overlying each of the photodiodes.

18. The method of claim 14 further comprising forming a respective shallow trench isolation (STI) region between pairs of laterally adjacent photodiodes.

19. The method of claim 14 further comprising forming an oxide layer overlying the second well.

20. The method of claim 14 wherein the superlattice further comprises a semiconductor cap layer thereon.

Assignees

• Atomera Inc

Inventors

• Chen Yi-Ann
• Husain Abid
• Takeuchi Hideki

Classifications

• H01L31/035254 Primary

  Electricity · mapped topic

• H01L27/14621

  Electricity · mapped topic

• H01L27/1463

  Electricity · mapped topic

• H01L27/1461

  Electricity · mapped topic

• H01L31/109

  Electricity · mapped topic