Structure and formation method of semiconductor device structure with nanowires

Patent metadata

Field	Value
Publication number	US-10374059-B2
Application number	US-201715692124-A
Country	US
Kind code	B2
Filing date	Aug 31, 2017
Priority date	Aug 31, 2017
Publication date	Aug 6, 2019
Grant date	Aug 6, 2019

Abstract

Structures and formation methods of a semiconductor device structure are provided. The method includes providing a substrate having a base portion and a fin portion over the base portion. The fin portion has a channel region and a source/drain region. The method also includes forming a stack structure over the fin portion. The stack structure includes first and second semiconductor layers. The method also includes forming a source/drain portion in the stack structure at the source/drain region, and removing a portion of the second semiconductor layer in the channel region in an etching process. The remaining portion of the first semiconductor layer in the channel region forms a nanowire. The method further includes forming a gate dielectric layer surrounding the nanowire, forming a high-k dielectric layer surrounding the gate dielectric layer, and forming a gate electrode surrounding the high-k dielectric layer.

First claim

What is claimed is:

1. A method for forming a semiconductor device structure,
comprising:
providing a substrate having a base portion and a fin portion over the base portion, wherein the fin portion has a channel region and a source/drain region;
forming a stack structure over the fin portion, wherein the stack structure comprises a first semiconductor layer and a second semiconductor layer vertically stacked over the fin portion;
forming a first protective layer covering the stack structure;
forming a source/drain portion in the stack structure at the source/drain region, wherein the first protective layer is formed before forming the source/drain portion;
removing a portion of the second semiconductor layer in the channel region in an etching process, wherein a remaining portion of the first semiconductor layer in the channel region forms a nanowire;
forming a gate dielectric layer surrounding the nanowire;
forming a high-k dielectric layer surrounding the gate dielectric layer; and
forming a gate electrode surrounding the high-k dielectric layer.

2. The method as claimed in claim 1 , wherein the semiconductor device structure has an input-output region and a core region, wherein the nanowire surrounded by the gate dielectric layer is positioned in the input-output region.

3. The method as claimed in claim 1 , wherein after formation of the gate dielectric layer, the method further comprises:
performing an annealing process on the gate dielectric layer.

4. The method as claimed in claim 1
wherein before removing the portion of the second semiconductor layer in the channel region, the method further comprises:
removing the first protective layer in the channel region.

5. The method as claimed in claim 1 , wherein after formation of the nanowire, the method further comprises:
forming a second protective layer surrounding the nanowire in the channel region, wherein the gate dielectric layer surrounds the second protective layer.

6. The method as claimed in claim 5 , wherein before forming the high-k dielectric layer, the method further comprises:
forming an additional layer surrounding the gate dielectric layer, wherein the high-k dielectric layer surrounds the additional layer.

7. The method as claimed in claim 1 , wherein the stack structure comprises a plurality of the first semiconductor layers and a plurality of the second semiconductor layers alternately stacked vertically over the fin portion,
wherein the etching process removes portions of the plurality of the second semiconductor layers in the channel region, and the remaining portions of the plurality of the first semiconductor layers in the channel region form a plurality of the nanowires.

8. The method as claimed in claim 7 , wherein the nanowires are vertically spaced apart from each other by a first distance, wherein the first distance is substantially equal to a thickness of the second semiconductor layer.

9. The method as claimed in claim 1 , wherein a thickness of the first semiconductor layer is substantially equal to a thickness of the second semiconductor layer.

10. The method as claimed in claim 1 , wherein the etching process further removes an upper portion of the fin portion of the substrate.

11. A method for forming a semiconductor device structure, comprising:
forming a first stack structure over a first fin portion in an input-output region of a substrate and a second stack structure over a second fin portion in a core region of the substrate;
forming a first source/drain portion in the first stack structure and a second source/drain portion in the second stack structure;
removing a portion of the first stack structure to form a first nanowire in the input-output region;
removing a portion of the second stack structure to form a second nanowire in the core region;
forming a dielectric layer surrounding the first nanowire;
annealing the dielectric layer after the first nanowire is formed;
forming a first gate structure surrounding the dielectric layer and the first nanowire, wherein the first gate structure is adjacent to the first source/drain portion; and
forming a second gate structure surrounding the second nanowire, wherein the second gate structure is adjacent to the second source/drain portion.

12. The method as claimed in claim 11 , further comprising:
forming a first protective layer between the dielectric layer and the first nanowire; and
forming a second protective layer between the second gate structure and the second nanowire.

13. The method as claimed in claim 12 , further comprising:
forming a second additional layer between the second protective layer and the second gate structure in the core region.

14. The method as claimed in claim 13 , further comprising:
forming a high-k dielectric layer surrounding the dielectric layer, wherein the second additional layer is surrounded by the high-k dielectric layer in the core region.

15. The method as claimed in claim 11 , further comprising:
forming a first additional layer between the dielectric layer and the first gate structure in the input-output region.

16. A method for forming a semiconductor device structure, comprising:
forming a stack structure over a substrate;
forming a dummy gate structure over the stack structure, wherein the dummy gate structure has a dummy gate dielectric layer and a dummy gate electrode over the gate dielectric layer;
forming a source/drain portion in the stack structure;
forming an interlayer dielectric layer over the source/drain portion;
forming a protective element over the interlayer dielectric layer;
removing a portion of the stack structure to form a nanowire; and
replacing the dummy gate structure with a gate structure, wherein the gate structure has a gate electrode and a gate dielectric layer surrounded by the gate electrode, the gate dielectric and the gate dielectric layer is thicker than the dummy gate dielectric layer, and
wherein the nanowire is surrounded by the gate structure.

17. The method as claimed in claim 16 , further comprising:
removing a portion of the interlayer dielectric layer, wherein the protective element is formed over a remaining portion of the interlayer dielectric layer, and the protective element is formed before the nanowire.

18. The method as claimed in claim 16 , further comprising:
forming an etch stop layer over the source/drain portion, wherein the interlayer dielectric layer is above the etch stop layer, and the protective element is disposed between two sidewalls of the etch stop layer.

19. The method as claimed in claim 16 , wherein a material of the protective element is different from a material of the interlayer dielectric layer.

20. The method as claimed in claim 16 , further comprising:
forming a protective layer between the nanowire and the gate structure; and
performing a clean process before forming the protective layer, wherein the interlayer dielectric layer is protected by the protective element during the clean process.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Cheng Chao-Ching
• Yun Wei-Sheng
• Yu Shao-Ming
• Lee Tsung-Lin
• Yeh Chih-Chieh

Classifications

• H10W10/0121 Primary

  in regions recessed from the surface, e.g. in trenches or grooves · CPC title

• H10W10/13

  formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI] · CPC title

• B82Y10/00

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• H01L29/0649

  Electricity · mapped topic

• H01L29/42356

  Electricity · mapped topic