Multi-Gate Device and Method of Fabrication Thereof

Patent metadata

Field	Value
Publication number	US-2017194213-A1
Application number	US-201514983816-A
Country	US
Kind code	A1
Filing date	Dec 30, 2015
Priority date	Dec 30, 2015
Publication date	Jul 6, 2017
Grant date	—

Abstract

A method of semiconductor device fabrication is described that includes forming a first fin extending from a substrate. The first fin has a source/drain region and a channel region and the first fin is formed of a first stack of epitaxial layers that includes first epitaxial layers having a first composition interposed by second epitaxial layers having a second composition. The method also includes removing the second epitaxial layers from the source/drain region of the first fin to form first gaps, covering a portion of the first epitaxial layers with a dielectric layer and filling the first gaps with the dielectric material and growing another epitaxial material on at least two surfaces of each of the first epitaxial layers to form a first source/drain feature while the dielectric material fills the first gaps.

First claim

1 . A method comprising:
forming a first fin extending from a substrate, the first fin having a source/drain region and a channel region, wherein the first fin is formed of a first stack of epitaxial layers that includes first epitaxial layers having a first composition interposed by second epitaxial layers having a second composition; removing the second epitaxial layers from the source/drain region of the first fin to form first gaps; covering a portion of the first epitaxial layers with a dielectric layer and filling the first gaps with the dielectric material; and growing another epitaxial material on at least two surfaces of each of the first epitaxial layers to form a first source/drain feature while the dielectric material fills the first gaps, wherein the another epitaxial material physically contacts the at least two surfaces of each of the first epitaxial layers.

2 . The method of claim 1 , further comprising:
forming a third epitaxial layer underlying the first epitaxial layers; oxidizing the third epitaxial layer to form an oxidized third epitaxial layer; wherein the oxidized third epitaxial layer underlies a gate on the channel region and the source/drain feature.

3 . The method of claim 1 , further comprising:
removing the second epitaxial layers from the first stack in the channel region of the first fin to form another gap; and forming a gate structure over the first epitaxial layers in the channel region, wherein the gate structure is disposed over top, bottom and opposing lateral sides of the first epitaxial layer.

4 . The method of claim 1 , wherein covering the portion of the first epitaxial layers with the dielectric layer and filling the first gaps with the dielectric material includes:
forming the dielectric layer over the first stack; and removing the dielectric layer from a top surface and sidewall surfaces of the first stack.

5 . The method of claim 1 , further comprising:
forming a second fin extending from the substrate, the second fin having a source/drain region and a channel region, wherein the second fin is formed of a second stack of epitaxial layers that includes first epitaxial layers having the first composition interposed by second epitaxial layers having the second composition; removing the second epitaxial layers from the source/drain region of the second fin to form second gaps; covering a lower portion of the second stack with the dielectric layer and filling the second gaps in an upper portion of the second stack with the dielectric material, the upper portion of the second stack includes different amount of first epitaxial layers than an upper portion of the first stack; and growing another epitaxial material on at least two surfaces of each of the first epitaxial layers to form a second source/drain feature while the dielectric material is filling the second gaps.

6 . The method of claim 5 , wherein covering the lower portion of the second stack with the dielectric layer and filling the second gaps in the upper portion of the second stack with the dielectric material includes:
forming the dielectric layer over the second stack during covering the portion of the first epitaxial layers with the dielectric layer and filling the first gaps with the dielectric material; and removing the dielectric layer from a top surface and sidewalls of the upper portion of the second stack during removing the dielectric layer from the top surface and sidewalls of the upper portion of the first stack.

7 . The method of claim 5 , wherein covering the lower portion of the second stack with the dielectric layer and filling the second gaps in the upper portion of the second stack with the dielectric material includes removing the dielectric layer from a top surface and sidewalls of the upper portion of the second stack while covering the first stack with another hard mask.

8 . The method of claim 1 , wherein the first composition includes silicon and the second composition includes silicon germanium.

9 . A method comprising:
forming a first fin extending from a substrate, the first fin having a first source and drain region and a first channel region, wherein the first fin includes a first stack of epitaxial layers that includes first epitaxial layers having a first composition interposed by second epitaxial layers having a second composition; forming a second fin extending from the substrate, the second fin having a second source and drain region and a second channel region, wherein the second fin includes a second stack of epitaxial layers that includes first epitaxial layers having the first composition interposed by second epitaxial layers having the second composition; removing the second epitaxial layers from the first source/drain region to form first gaps and from the second source/drain region to form second gaps; covering a lower portion of the first stack with a dielectric layer and filling the first gaps in an upper portion of the first stack with the dielectric material; covering a lower portion of the second stack with the dielectric layer and filling the second gaps in an upper portion of the second stack with the dielectric material, wherein the upper portion of the second stack includes different amount of first epitaxial layers than the upper portion of the first stack; and growing another epitaxial material on at least two surfaces of each of the first epitaxial layers to form a first source/drain feature and a second source/drain feature, respectively, while the dielectric material fills the first gaps and second gaps, wherein the another epitaxial material physically contacts the at least two surfaces of each of the first epitaxial layers.

10 . The method of claim 9 , further comprising:
forming a third epitaxial layer underlying the first epitaxial layers of the first fin; and oxidizing the third epitaxial layer to form an oxidized third epitaxial layer.

11 . The method of claim 9 , further comprising:
removing the second epitaxial layers from the first stack in the first channel region and the second stack in the second channel region to form another gaps; and forming gate structures over the first epitaxial layers in the another gaps, wherein the gate structures are disposed over top, bottom and opposing lateral sides of the first epitaxial layers in the first and second channel regions.

12 . The method of claim 9 , wherein covering the lower portion of the first stack with the dielectric layer and filling the gaps in the upper portion of the first stack with the dielectric material includes:
forming the dielectric layer over the first stack; and removing the dielectric layer from a top surface and sidewalls of the upper portion of the first stack.

13 . The method of claim 12 , wherein covering the lower portion of the second stack with the dielectric layer and filling the second gaps in the upper portion of the second stack with the dielectric material includes:
forming the dielectric layer over the second stack during forming the dielectric layer over the first stack; removing the dielectric layer from a top surface and sidewalls of the upper portion of the second stack during removing the dielectric layer from the top surface and sidewalls of the upper portion of the first stack; and etching back further the dielectric layer from sidewalls of the upper portion of the second stack while covering the first stack with a hard mask.

14 . The method of claim 12 , wherein covering the lower portion of the second stack with the dielectric layer and filling the second gaps in the upper portion of the second stack with the dielectric material inc

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Ching Kuo-Cheng
• Tsai Ching-Wei
• Diaz Carlos H
• Wang Chih-Hao
• Lien Wai-Yi
• Leung Ying-Keung

Classifications

• H10D84/8312

  the IGFETs characterised by having different source or drain region structures, e.g. IGFETs having symmetrical source or drain regions integrated with IGFETs having asymmetrical source or drain regions · CPC title

• H10D84/8311

  the IGFETs characterised by having different channel structures · CPC title

• H01L27/0924

  Electricity · mapped topic

• H01L29/42392

  Electricity · mapped topic

• H01L21/823807

  Electricity · mapped topic