Overlay mark and method for forming the same

Patent metadata

Field	Value
Publication number	US-2016093573-A1
Application number	US-201414498217-A
Country	US
Kind code	A1
Filing date	Sep 26, 2014
Priority date	Sep 26, 2014
Publication date	Mar 31, 2016
Grant date	—

Abstract

An overlay mark applied to a LELE-type double patterning lithography (DPL) process including a first lithography step, a first etching step, a second lithography step and a second etching step in sequence is described. The overlay mark includes a first x-directional pattern and a first y-directional pattern of a previous layer, second x-directional and y-directional patterns of a current layer defined by the first lithography step, and third x-directional and y-directional patterns of the current layer defined by the second lithography step. The second x-directional patterns and the third x-directional patterns are arranged alternately beside the first x-directional pattern. The second y-directional patterns and the third y-directional patterns are arranged alternately beside the first y-directional pattern.

First claim

1 . An overlay mark applied to a double patterning lithography (DPL) process including a first lithography step, a first etching step, a second lithography step and a second etching step in sequence, comprising:
a first x-directional pattern and a first y-directional pattern of a previous layer; a plurality of second x-directional patterns and a plurality of second y-directional patterns of a current layer, defined by the first lithography step; and a plurality of third x-directional patterns and a plurality of third y-directional patterns of the current layer, defined by the second lithography step, wherein the second x-directional patterns and the third x-directional patterns are arranged alternately beside the first x-directional pattern, and the second y-directional patterns and the third y-directional patterns are arranged alternately beside the first y-directional pattern.

2 . The overlay mark of claim 1 , wherein among a first group including the first x-directional pattern and the first y-directional pattern, a second group including the second x-directional patterns and the second y-directional patterns, and a third group including the third x-directional patterns and the third y-directional patterns, each group independently has a trench form or a solid line form for each pattern in the group.

3 . The overlay mark of claim 1 , wherein among a first group including the first x-directional pattern and the first y-directional pattern, a second group including the second x-directional patterns and the second y-directional patterns, and a third group including the third x-directional patterns and the third y-directional patterns, each group independently has a linear shape or a non-linear shape for each pattern in the group.

4 . The overlay mark of claim 1 , wherein the previous layer comprises a conductive layer to be electrically connected with, and the current layer comprises an insulating layer covering the conductive layer.

5 . The overlay mark of claim 4 , wherein the conductive layer comprises doped polysilicon.

6 . The overlay mark of claim 4 , wherein the DPL process is for forming dense contact openings in the insulating layer.

7 . The overlay mark of claim 4 , wherein the third x-directional patterns and the third y-directional patterns of the current layer defined by the second lithography step are all trench patterns in a photoresist layer.

8 . The overlay mark of claim 4 , wherein the second x-directional patterns and the second y-directional patterns defined by the first lithography step are all formed in a hard mask layer.

9 . The overlay mark of claim 8 , wherein the hard mask layer comprises an advanced patterning film (APF), silicon nitride (SiN), or titanium nitride (TiN).

10 . A method for forming an overlay mark applied to a double patterning lithography (DPL) process including a first lithography step, a first etching step, a second lithography step and a second etching step in sequence, comprising:
forming a first x-directional pattern and a first y-directional pattern of a previous layer; defining, in the first lithography step, a plurality of second x-directional patterns and a plurality of second y-directional patterns of a current layer in a first photoresist layer; measuring first overlay errors between the second x-directional patterns and the first x-directional pattern and between the second y-directional patterns and the first y-directional pattern, and retaining the first photoresist layer if the first overlay errors are acceptable; transferring, in the first etching step, the second x-directional patterns and the second y-directional patterns to a hard mask layer over the previous layer; defining, in the second lithography step, a plurality of third x-directional patterns and a plurality of third y-directional patterns of the current layer in a second photoresist layer; and measuring second overlay errors between the third x-directional patterns and the first x-directional pattern and between the third y-directional patterns and the first y-directional pattern, and retaining the second photoresist layer if the second overlay errors are acceptable, wherein the second x-directional patterns and the third x-directional patterns are arranged alternately beside the first x-directional pattern, and the second y-directional patterns and the third y-directional patterns are arranged alternately beside the first y-directional pattern.

11 . The method of claim 10 , wherein among a first group including the first x-directional pattern and the first y-directional pattern, a second group including the second x-directional patterns and the second y-directional patterns, and a third group including the third x-directional patterns and the third y-directional patterns, each group independently has a trench form or a solid line form for each pattern in the group.

12 . The method of claim 10 , wherein among a first group including the first x-directional pattern and the first y-directional pattern, a second group including the second x-directional patterns and the second y-directional patterns, and a third group including the third x-directional patterns and the third y-directional patterns, each group independently has a linear shape or a non-linear shape for each pattern in the group.

13 . The method of claim 10 , wherein the previous layer comprises a conductive layer to be electrically connected with, and the current layer comprises an insulating layer that covers the conductive layer and is under the hard mask layer.

14 . The method of claim 13 , wherein the conductive layer comprises doped polysilicon.

15 . The method of claim 13 , wherein the DPL process is for forming dense contact openings in the insulating layer.

16 . The method of claim 13 , wherein the third x-directional patterns and the third y-directional patterns of the current layer defined in the second lithography step are all trenches patterns in the second photoresist layer.

17 . The method of claim 13 , wherein in transferring the second x-directional patterns and the second y-directional patterns to the hard mask layer in the first etching step, the etching is continued into the insulating layer under the hard mask layer.

18 . The method of claim 10 , wherein in measuring each of the first or second overlay errors, positions of two outmost patterns of the second x- or y-directional patterns or of the third x- or y-directional patterns are measured.

19 . The method of claim 10 , wherein the hard mask layer comprises an advanced patterning film (APF), silicon nitride (SiN), or titanium nitride (TiN).

Assignees

• United Microelectronics Corp

Inventors

• Liou En-Chiuan
• Kuo Teng-Chin
• Chen Yi-Ting

Classifications

• H10P74/203

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

• H10P74/23

  characterised by multiple measurements, corrections, marking or sorting processes · CPC title

• H10W46/301

  for alignment · CPC title

• H10W20/4451

  Semiconductor materials, e.g. polysilicon · CPC title

• H10W46/00 Primary

  Marks applied to devices, e.g. for alignment or identification · CPC title