Semiconductor device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-10325911-B2
Application number	US-201715696573-A
Country	US
Kind code	B2
Filing date	Sep 6, 2017
Priority date	Dec 30, 2016
Publication date	Jun 18, 2019
Grant date	Jun 18, 2019

Abstract

In a method of manufacturing a semiconductor device, an interlayer dielectric (ILD) layer is formed over an underlying structure. The underlying structure includes a gate structure disposed over a channel region of a fin structure, and a first source/drain epitaxial layer disposed at a source/drain region of the fin structure. A first opening is formed over the first source/drain epitaxial layer by etching a part of the ILD layer and an upper portion of the first source/drain epitaxial layer. A second source/drain epitaxial layer is formed over the etched first source/drain epitaxial layer. A conductive material is formed over the second source/drain epitaxial layer.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, the method comprising:
forming an interlayer dielectric (ILD) layer over an underlying structure, the underlying structure including:
a gate structure disposed over a channel region of a fin structure; and
a first source/drain epitaxial layer disposed at a source/drain region of the fin structure, wherein the first source/drain epitaxial layer is formed in and above a recess disposed in the fin structure;

forming a first opening over the first source/drain epitaxial layer by etching a part of the ILD layer and an upper portion of the first source/drain epitaxial layer;
forming a second source/drain epitaxial layer over the etched first source/drain epitaxial layer; and
forming a conductive material over the second source/drain epitaxial layer.

2. The method of claim 1 , wherein:
the underlying structure further includes an etch-stop layer, and
in the forming the first opening, a part of the etch-stop layer is also etched.

3. The method of claim 1 , further comprising, after the forming the second source/drain epitaxial layer:
forming a metal layer over the second source/drain epitaxial layer; and
forming a silicide layer by reacting the metal layer and the second source/drain epitaxial layer,
wherein the conductive material is formed on the silicide layer.

4. The method of claim 3 , further comprising, before the forming the metal layer, performing an implantation operation on the second source/drain epitaxial layer.

5. The method of claim 1 , further comprising, after the forming the first opening:
forming a cover layer in the first opening and over the ILD layer; and
patterning the cover layer, thereby forming a second opening in the cover layer,
wherein the second source/drain epitaxial layer is formed in the second opening.

6. The method of claim 1 , wherein the first source/drain epitaxial layer has a different composition than the second source/drain epitaxial layer.

7. The method of claim 1 , wherein:
the first source/drain epitaxial layer and the second source/drain epitaxial layer contain Ge, and
a concentration of Ge in the second source/drain epitaxial layer is higher than a concentration of Ge in the first source/drain epitaxial layer.

8. The method of claim 7 , wherein at least one of the first source/drain epitaxial layer and the second source/drain epitaxial layer further contains B.

9. The method of claim 1 , wherein the second source/drain epitaxial layer includes one selected from the group consisting of SiP, InP and GaInP.

10. A method of manufacturing a semiconductor device, the method comprising:
forming an interlayer dielectric (ILD) layer over an underlying structure, the underlying structure including:
a first gate structure and a first source/drain epitaxial layer for a first conductivity-type fin field effect transistor (FinFET); and
a second gate structure and a second source/drain epitaxial layer for a second conductivity-type fin field effect transistor (FinFET);

forming a first opening over the first source/drain epitaxial layer by etching a part of the ILD layer and an upper portion of the first source/drain epitaxial layer, and a second opening over the second source/drain epitaxial layer by etching a part of the ILD layer and an upper portion of the second source/drain epitaxial layer; and
forming a third source/drain epitaxial layer over the etched first source/drain epitaxial layer, while covering the second opening with a first cover layer.

11. The method of claim 10 , further comprising:
removing the first cover layer; and
forming a fourth source/drain epitaxial layer over the etched second source/drain epitaxial layer, while covering the third source/drain epitaxial layer with a second cover layer.

12. The method of claim 11 , further comprising, after the forming the fourth source/drain epitaxial layer:
removing the second cover layer;
forming a metal layer over the third and fourth source/drain epitaxial layers;
forming a first silicide layer by reacting the metal layer and the third source/drain epitaxial layer and forming a second silicide layer by reacting the metal layer and the fourth source/drain epitaxial layer; and
forming a first contact layer on the first silicide layer and a second contact layer on the second silicide layer.

13. The method of claim 11 , wherein:
the first cover layer is formed in the first opening and over the ILD layer,
the method further comprises patterning the first cover layer formed in the first opening, thereby forming a third opening in the first cover layer, and
the third source/drain epitaxial layer is formed in the third opening.

14. The method of claim 13 , wherein:
the second cover layer is also formed in the second opening and over the ILD layer,
the method further comprises patterning the second cover layer formed in the second opening, thereby forming a fourth opening in the second cover layer, and
the fourth source/drain epitaxial layer is formed in the fourth opening.

15. The method of claim 11 , wherein:
the first source/drain epitaxial layer has a different composition than the third source/drain epitaxial layer, and
the second source/drain epitaxial layer has a different composition than the fourth source/drain epitaxial layer.

16. The method of claim 11 , wherein:
the first conductivity-type is p-type,
the first source/drain epitaxial layer and the third source/drain epitaxial layer contain Ge, and
a concentration of Ge in the third source/drain epitaxial layer is higher than a concentration of Ge in the first source/drain epitaxial layer.

17. The method of claim 16 , wherein at least one of the first source/drain epitaxial layer and the third source/drain epitaxial layer further contains B.

18. The method of claim 11 , wherein:
the first conductivity-type is an n-type, and
the third source/drain epitaxial layer includes one selected from the group consisting of SiP, InP and GaInP.

19. A method of manufacturing a semiconductor device, the method comprising:
forming an interlayer dielectric (ILD) layer over an underlying structure, the underlying structure including:
a gate structure disposed over a channel region of a first fin structure and a channel region of a second fin structure;
a first source/drain epitaxial layer disposed at a source/drain region of the first fin structure; and
a second source/drain epitaxial layer disposed at a source/drain region of the second fin structure;

forming a first opening over the first and second source/drain epitaxial layers by etching a part of the ILD layer and upper portions of the first and second source/drain epitaxial layers;
forming a third source/drain epitaxial layer over the etched first and second source/drain epitaxial layers; and
forming a conductive material over the third source/drain epitaxial layer.

20. A method of manufacturing a semiconductor device, the method comprising:
forming an interlayer dielectric (ILD) layer over an underlying structure, the underlying structure including:
a gate structure disposed over a channel region of a fin structure; and
a first source/drain epitaxial layer disposed at a source/drain region of the fin structure;

forming a first opening over the first source/drain epitaxial layer by etching a part of the ILD layer and an upper portion of the first source/drain epitaxial layer;
forming a cover layer in the first opening and over the ILD layer;
patterning the cover layer, thereby

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lu Wei-Yuan
• Yeong Sai-Hooi

Classifications

• H10D64/0112

  using conductive layers comprising silicides · CPC title

• H10D64/0113 Primary

  the conductive layers comprising highly doped semiconductor materials, e.g. polysilicon layers or amorphous silicon layers · CPC title

• H10W20/076

  in via holes or trenches · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10P50/00

  Etching of wafers, substrates or parts of devices · CPC title