Method for fabricating semiconductor device

Patent metadata

Field	Value
Publication number	US-9324610-B2
Application number	US-201414455939-A
Country	US
Kind code	B2
Filing date	Aug 10, 2014
Priority date	Jul 8, 2014
Publication date	Apr 26, 2016
Grant date	Apr 26, 2016

Abstract

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having at least one metal gate thereon, a source/drain region adjacent to two sides of the at least one metal gate, and an interlayer dielectric (ILD) layer around the at least one metal gate; forming a plurality of contact holes in the ILD layer to expose the source/drain region; forming a first metal layer in the contact holes; performing a first thermal treatment process; and performing a second thermal treatment process.

First claim

What is claimed is:

1. A method for fabricating semiconductor device, comprising:
providing a substrate having at least one metal gate thereon, a source/drain region adjacent to two sides of the at least one metal gate, a contact etch stop layer (CESL) around the at least one metal gate, and an interlayer dielectric (ILD) layer around the at least one metal gate, wherein the metal gate comprises a work function metal layer and a low resistance metal layer;
removing part of the ILD layer to form a plurality of contact holes exposing the source/drain region, the CESL, and the metal gate;
forming a first metal layer and a second metal layer in the contact holes, wherein the first metal layer contacts the CESL directly;
performing a first thermal treatment process after forming the first metal layer and the second metal layer; and
performing a second thermal treatment process to form a silicide on the source/drain region while no silicide is formed on the metal gate.

2. The method of claim 1 , further comprising:
forming a fin-shaped structure on the substrate; and
forming the at least one metal gate on the fin-shaped structure.

3. The method of claim 1 , wherein the first thermal treatment process comprises a soak anneal process, and the second thermal treatment process comprises a spike anneal process.

4. The method of claim 1 , wherein the temperature of the first thermal treatment process is between 500° C. to 600° C.

5. The method of claim 1 , wherein the temperature of the second thermal treatment process is between 600° C. to 950° C.

6. The method of claim 1 , wherein the duration of the first thermal treatment process is between 10 seconds to 60 seconds.

7. The method of claim 1 , wherein the duration of the second thermal treatment process is between 100 milliseconds to 5 seconds.

8. The method of claim 1 , further comprising forming a second metal layer after forming the first metal layer.

9. The method of claim 8 , wherein the first metal layer is selected from the group consisting of Ti, Co, Ni, and Pt, and the second metal layer comprises TiN.

10. The method of claim 8 , further comprising:
forming an epitaxial layer on the source/drain region;
forming a dielectric layer on the ILD layer;
forming the contact holes in the dielectric layer and the ILD layer;
forming the first metal layer and the second metal layer in the contact holes;
performing the first thermal treatment process and the second thermal treatment process for forming the silicide on the epitaxial layer;
forming a third metal layer to fill the contact holes; and
performing a planarizing process to partially remove the third metal layer, the second metal layer, and the first metal layer.

11. The method of claim 10 , wherein the third metal layer comprises tungsten.

12. The method of claim 10 , wherein the silicide comprises a C54 phase structure.

13. The method of claim 1 , further comprising performing a pre-clean process before forming the first metal layer.

14. A semiconductor device, comprising:
a substrate;
a metal gate on the substrate;
a contact etch stop layer (CESL) around the metal gate;
a source/drain region adjacent to the metal gate in the substrate;
an interlayer dielectric (ILD) layer on the substrate and around the metal gate;
a plurality of contact plugs electrically connected to the source/drain region and the metal gate, wherein each of the contact plugs comprises a first metal layer surrounding a second metal layer and a third metal layer; and
a silicide between the contact plugs and the source/drain region, wherein the silicide comprises a C54 phase structure and the CESL, the first metal layer, the second metal layer, and the third metal layer are all disposed on the silicide, and two sides of the silicide are aligned with two edges of the CESL.

15. The semiconductor device of claim 14 , further comprising a fin-shaped structure between the substrate and the metal gate.

16. The semiconductor device of claim 14 , further comprising an epitaxial layer between the silicide and the source/drain region.

17. The semiconductor device of claim 14 , wherein the second metal layer directly contacts the silicide.

18. The semiconductor device of claim 14 , wherein the first metal layer is selected from the group consisting of Ti, Co, Ni, and Pt, the second metal layer comprises TiN, and the third metal layer comprises W.

Assignees

• United Microelectronics Corp

Inventors

• Hung Ching-Wen
• Wu Jia-Rong
• Chang Tsung-Hung
• Lin Ching-Ling
• Lee Yi-Hui
• Huang Chih-Sen
• Chen Yi-Wei
• Lin Chun-Hsien

Classifications

• H10D64/0112

  using conductive layers comprising silicides · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/047

  by introducing additional elements therein · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10W20/033

  in openings in dielectrics · CPC title