Semiconductor device and method for fabricating the same

Patent metadata

Field	Value
Publication number	US-9899522-B1
Application number	US-201715401092-A
Country	US
Kind code	B1
Filing date	Jan 8, 2017
Priority date	Dec 13, 2016
Publication date	Feb 20, 2018
Grant date	Feb 20, 2018

Abstract

A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a first recess adjacent to two sides of the gate structure; forming an epitaxial layer in the first recess; removing part of the epitaxial layer to forma second recess; and forming an interlayer dielectric (ILD) layer on the gate structure and into the second recess.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate;
a gate structure on the substrate;
a first recess adjacent to two sides of the gate structure;
an epitaxial layer in the first recess, wherein the epitaxial layer comprises a top surface extending along a first direction and a sidewall extending along a second direction; and
a contact etch stop layer (CESL) on the epitaxial layer and in the first recess and directly contacting the top surface and the sidewall of the epitaxial layer.

2. The semiconductor device of claim 1 , further comprising:
a second recess in the epitaxial layer; and
the CESL in the second recess.

3. The semiconductor device of claim 1 , wherein the CESL contacts the epitaxial layer in the first recess.

4. The semiconductor device of claim 1 , further comprising an interlayer dielectric (ILD) layer on the CESL.

5. The semiconductor device of claim 4 , further comprising a contact plug in the ILD layer and in the first recess.

6. The semiconductor device of claim 5 , wherein the contact plug contacts the CESL and the epitaxial layer in the first recess.

7. The semiconductor device of claim 5 , wherein the contact plug contacts the CESL above a top surface of the substrate and below the top surface of the substrate.

8. The semiconductor device of claim 1 , wherein the first direction is orthogonal to the second direction.

Assignees

• United Microelectronics Corp

Inventors

• Liu An Chi
• Lin Chun Hsien

Classifications

• H10D64/0112

  using conductive layers comprising silicides · CPC title

• H10P14/40

  of conductive or resistive materials · CPC title

• H10W20/083

  the openings being via holes penetrating underlying conductors · CPC title

• H10W20/047

  by introducing additional elements therein · CPC title

• H10W20/033

  in openings in dielectrics · CPC title