Method for manufacturing an encapsulation cover for an electronic package and electronic package comprising a cover

US10325784B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10325784-B2
Application numberUS-201715685552-A
CountryUS
Kind codeB2
Filing dateAug 24, 2017
Priority dateJan 3, 2017
Publication dateJun 18, 2019
Grant dateJun 18, 2019

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method for manufacturing a cover for an electronic package includes placing an insert having opposite faces between opposite faces of a cavity of a mold. A coating material is injected in the mold cavity around the insert. The coating material is then set to form a substrate that is overmolded around the insert and produce the cover.

First claim

Opening claim text (preview).

The invention claimed is: 1. An electronic package, comprising: a carrier substrate; an electronic chip having a back face fixed to a front mounting face of the carrier substrate; and an encapsulation cover comprising: a substrate having a front face and a through passage; and an insert which is contained within the through passage and has a front face which is coplanar with the front face of the substrate, wherein said encapsulation cover is mounted to the front mounting face of said carrier substrate by way of an adhesive interposed between a peripheral zone of the carrier substrate and a peripheral zone of a back face of said substrate such that the insert of the encapsulation cover is positioned above a front face of the electronic chip. 2. The package according to claim 1 , wherein the adhesive is an annular bead of adhesive. 3. The package according to claim 1 , wherein the adhesive is an annular strip of adhesive. 4. The package according to claim 1 , where said substrate includes a ring-shaped rib surrounding said electronic chip at a distance, the encapsulation cover being mounted to said front mounting face of the carrier substrate at a rear face of said ring-shaped rib. 5. The package according to claim 1 , wherein said insert has a back face that is wholly covered by said substrate. 6. The package according to claim 5 , wherein said insert has a back face that is at least partly uncovered by said substrate. 7. The package according to claim 6 , wherein said insert comprises a portion that protrudes backwards facing the front face of the electronic chip, said portion being at least partly uncovered by said substrate. 8. The package according to claim 7 , wherein said portion that protrudes backward has a surface that is mounted to the front face of the electronic chip by way of a layer of adhesive. 9. The package according to claim 1 , wherein said insert is made of a heat conducting material. 10. The package according to claim 1 , wherein said insert is made of a material configured to form an electromagnetic protection screen. 11. The package according to claim 1 , wherein said insert comprises a substrate. 12. The package according to claim 1 , wherein said insert comprises a grating.

Assignees

Inventors

Classifications

  • Die-attach connectors and bond wires · CPC title

  • batch processes · CPC title

  • Subject matter not provided for in other groups of this subclass · CPC title

  • Seals · CPC title

  • Solid or gel fillings · CPC title

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Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US10325784B2 cover?
A method for manufacturing a cover for an electronic package includes placing an insert having opposite faces between opposite faces of a cavity of a mold. A coating material is injected in the mold cavity around the insert. The coating material is then set to form a substrate that is overmolded around the insert and produce the cover.
Who is the assignee on this patent?
St Microelectronics Grenoble 2
What technology area does this patent fall under?
Primary CPC classification H10W74/016. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jun 18 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).