Method for collective (wafer-scale) fabrication of electronic devices and electronic device

Patent metadata

Field	Value
Publication number	US-9870947-B1
Application number	US-201715632878-A
Country	US
Kind code	B1
Filing date	Jun 26, 2017
Priority date	Jul 1, 2016
Publication date	Jan 16, 2018
Grant date	Jan 16, 2018

Abstract

Electronic devices are manufactured using a collective (wafer-scale) fabrication process. Electronic chips are mounted onto one face of a collective substrate wafer. A collective flexible sheet made of a heat-conductive material comprising a layer containing pyrolytic graphite is fixed to extend over a collective region extending over the electronic chips and over the collective substrate wafer between the electronic chips. The collective flexible sheet is then compressed. A dicing operation is then carried out in order to obtain electronic devices each including an electronic chip, a portion of the collective plate and a portion of the collective flexible sheet.

First claim

What is claimed is:

1. A method for wafer-scale fabrication of electronic devices, comprising the following steps:
a) mounting a plurality of electronic chips onto a mounting face of a collective substrate wafer, said electronic chips being separated from one another and positioned on location sites,
b) extending a collective flexible sheet comprising at least one layer made of a heat-conductive material that contains pyrolytic graphite over a collective region running over the electronic chips and over the mounting face of the collective substrate wafer and between the electronic chips,
c) compressing the collective flexible sheet in the direction of the collective region, and
d) carrying out a dicing in order to obtain electronic devices respectively comprising at least one of the electronic chips, a portion of the collective substrate wafer corresponding to a location site and a portion of the collective flexible sheet corresponding to this location site.

2. The method according to claim 1 , comprising the following step between the step a) and the step b): forming a collective encapsulation block filling, at least in part, gaps between the electronic chips, the collective region comprising at least a part of back faces of the electronic chips and a back face of the collective encapsulation block.

3. The method according to claim 1 , comprising the following step between the step a) and the step b): forming encapsulation rings extending respectively around the electronic chips and over the mounting face of the substrate wafer, the collective region comprising at least a part of back faces of the electronic chips, at least a part of back faces of the encapsulation rings and at least a part of the mounting face of the collective substrate wafer which extend between the encapsulation rings.

4. The method according to claim 1 , comprising the following step after the step b) or the step c): forming a collective encapsulation block on top of the flexible sheet.

5. The method according to claim 1 , comprising the following step after the step b) or the step c): forming a collective protective layer on top of the collective flexible sheet.

6. The method according to claim 1 , comprising the following step between the steps a) and b): forming a collective protective layer on top of the region.

7. The method according to claim 1 , wherein the collective flexible sheet to be extended comprises the layer made of a heat-conductive material that contains pyrolytic graphite and a protective layer.

8. The method according to claim 1 , wherein the collective flexible sheet to be extended comprises the layer made of a heat-conductive material that contains pyrolytic graphite interposed between two protective layers.

9. The method according to claim 8 , wherein each protective layer exhibits a hardness greater than a hardness of the layer made of the heat-conductive material that contains pyrolytic graphite.

10. The method according to claim 8 , comprising the following step: fixing the collective flexible sheet on top of the collective region by means of a collective layer of adhesive.

11. An electronic device, comprising:
a substrate wafer having a mounting face,
at least one electronic chip having a front face mounted onto the mounting face of the substrate wafer, and
a flexible layer comprising at least one layer of a heat-conductive material that contains pyrolytic graphite, the flexible layer being situated on a region extending over a back face of the electronic chip and over the mounting face of the substrate wafer around the electronic chip.

12. The device according to claim 11 , comprising a layer of adhesive between the flexible layer and the region.

13. The device according to claim 11 , comprising a protective layer on top of the at least one layer of heat-conductive material that contains pyrolytic graphite.

14. The device according to claim 13 , in which the protective layer exhibits a hardness greater than the hardness of the at least one layer of heat-conductive material that contains pyrolytic graphite.

15. The device according to claim 11 , comprising a protective layer underneath the at least one layer of heat-conductive material that contains pyrolytic graphite.

16. The device according to claim 15 , in which the protective layer exhibits a hardness greater than the hardness of the at least one layer of heat-conductive material that contains pyrolytic graphite.

17. The device according to claim 11 , comprising an encapsulation block around the electronic chip and between the mounting face of the substrate wafer and the flexible layer, the region comprising the back face of the electronic chip and a back face of the encapsulation block.

18. The device according to claim 11 , comprising an encapsulation ring extending around the electronic chip and over the mounting face of the substrate wafer, the region comprising the back face of the electronic chip, a back face of the encapsulation ring and a part of the mounting face of the substrate wafer surrounding the encapsulation ring.

19. The device according to claim 11 , comprising an encapsulation block on top of the flexible layer.

Assignees

• Stmicroelectronics (Grenoble 2) Sas
• St Microelectronics Sa
• Commissariat Energie Atomique

Inventors

• Campos Didier
• Besancon Benoit
• Coudrain Perceval
• Colonna Jean-Philippe

Classifications

• H10P72/7402

  Wafer tapes, e.g. grinding or dicing support tapes · CPC title

• H10P58/00

  Singulating wafers or substrates into multiple chips, i.e. dicing · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W74/40

  characterised by their materials · CPC title