Array substrate, liquid crystal display panel and liquid crystal display device

Patent metadata

Field	Value
Publication number	US-10324348-B2
Application number	US-201816127767-A
Country	US
Kind code	B2
Filing date	Sep 11, 2018
Priority date	Jan 25, 2016
Publication date	Jun 18, 2019
Grant date	Jun 18, 2019

Abstract

The array substrate, the liquid crystal display panel and the liquid crystal display device of the present disclosure are designed to form the MIS storage capacitor by the P—Si semiconductor layer, the first metal layer and the insulating layer between above or the P—Si semiconductor layer, the second metal layer and the dielectric spacer layer between above, when one side of the first metal layer or the second metal layer receiving the negative gray voltage, the P—Si in the P—Si semiconductor layer will gather to form the hole, when receiving the positive gray voltage, will form the depletion layer on the upper layer of the P—Si to reduce the capacity of the MIS storage capacitor, thereby reducing the difference of the capacitance when the MIS storage capacitor in the positive and negative gray voltage, improving the flicker phenomena and ensuring the display effect.

First claim

What is claimed is:

1. An array substrate, comprising a substrate, and a first metal layer, an insulating layer, a polycrystalline silicon (P—Si) semiconductor layer, a dielectric spacer layer and a second metal layer that are formed on the substrate, wherein the first metal layer comprises a first zone and a second zone spaced from each other, the first zone of the first metal layer being a gate electrode of a thin film transistor (TFT) of the array substrate; the second metal layer comprises a third zone and a fourth zone arranged spaced from each other, the third zone and the fourth zone of the second metal layer being a source electrode and a drain electrode of the TFT, respectively, wherein the P—Si semiconductor layer and the second zone of the first metal layer are arranged insulated and overlapped through the insulating layer sandwiched between the P—Si semiconductor layer and the second zone of the first metal layer, or the P—Si semiconductor layer and the fourth zone of the second metal layer are arranged insulated and overlapped through the dielectric spacer layer sandwiched between the P—Si semiconductor layer and the fourth zone of the second metal layer to form a metal-insulator-semiconductor (MIS) storage capacitor of the array substrate;
wherein the gate electrode of the TFT is located under the P—Si semiconductor layer;
wherein the second metal layer further comprises a seventh zone that is spaced from and adjacent to the fourth zone and is distant from the third zone, the seventh zone of the second metal layer is in direct contact with the second zone of the first metal layer, and the P—Si semiconductor layer is in direct contact with the seventh zone of the second metal layer; and
wherein the P—Si semiconductor layer is connected to the second zone of the first metal layer by the seventh zone of the second metal layer so that the MIS storage capacitor of the array substrate is formed by the P—Si semiconductor layer, the fourth zone of the second metal, and the dielectric layer located there between.

2. The array substrate according to claim 1 , wherein the second zone of the first metal layer is across an active area of the array substrate, and the array substrate further comprises a common electrode arranged on the substrate, the second zone of the first metal layer being connected with the common electrode at a periphery of the active area.

3. The array substrate according to claim 1 , wherein the P—Si semiconductor layer comprises a P—Si layer after heavy doping treatment.

4. A liquid crystal display panel, comprising the array substrate as claimed in claim 1 .

5. A liquid crystal display device, comprising a liquid crystal display panel as claimed in claim 4 and a light source module providing light to the liquid crystal display panel.

6. The array substrate according to claim 1 , wherein the array substrate further comprises a common electrode arranged on the substrate, both the fourth zone and the seventh zone of the second metal layer are in contact with the common electrode by only a passivation layer, and the common electrode covers the fourth zone and the seventh zone of the second metal layer.

7. The array substrate according to claim 1 , wherein the seventh zone of the second metal layer passes through the dielectric spacer layer and the insulating layer, and is in direct contact with the second zone of the first metal layer.

8. The array substrate according to claim 1 , wherein the seventh zone of the second metal layer passes through the dielectric spacer layer and is in direct contact with the P—Si semiconductor layer.

Assignees

• Wuhan China Star Optoelectronics Technology Co Ltd

Inventors

• Yan Yao
• Cao Shangcao

Classifications

• H01L27/1255

  Electricity · mapped topic

• G02F2202/104

  poly-Si · CPC title

• H01L27/1222

  Electricity · mapped topic

• G02F1/134363

  for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS] · CPC title

• G02F1/136213

  Storage capacitors associated with the pixel electrode · CPC title