Array substrate, liquid crystal display panel and liquid crystal display device

Patent metadata

Field	Value
Publication number	US-10120249-B2
Application number	US-201615204906-A
Country	US
Kind code	B2
Filing date	Jul 7, 2016
Priority date	May 27, 2016
Publication date	Nov 6, 2018
Grant date	Nov 6, 2018

Abstract

The present application discloses an array substrate, a liquid crystal display panel and a liquid crystal display device; a metal layer is designed to be added between the pixel electrode and the common electrode. The metal layer can form a first storage capacitor with the pixel electrode and formed a second storage capacitor with the common electrode, such as the dual storage capacitors to enlarge the storage capacitor to improve the flicker caused by TFT leakage, ensure the display effect, and the two storage capacitor are overlapped set, the aperture ratio of the pixel is not reduced.

First claim

What is claimed is:

1. An array substrate, comprising: a substrate; a TFT, a planarization layer, a common electrode, a passivation layer and a pixel electrode sequentially formed on the substrate characterized in that the array substrate further comprising a touch panel insulation layer and a metal layer sequentially formed between the common electrode and the passivation layer; wherein the metal layer is electrically connected to the pixel electrode and the drain electrode of the TFT separately; by overlapping disposed, the insulation portion of the touch panel insulation layer and the passivation layer sandwiched by the common electrode and the pixel electrode to form the first storage capacitor; and by overlapping disposed, the insulation portion of the touch panel insulation layer sandwiched by the metal layer and the common electrode to form the second storage capacitor;
wherein the planarization layer and the touch panel insulation layer have a first contact hole to expose the drain electrode of the TFT and the metal layer is electrically connected to the drain electrode via the first contact hole; the passivation layer has a second contact hole to expose the metal layer and the pixel electrode is electrically connected to the metal layer via the second contact hole;
wherein the TFT comprises a shading metal layer, a buffer layer, a polycrystalline semiconductor layer, an insulating layer, a gate electrode, a dielectric isolation layer, and a source-drain electrode layer formed by a source electrode and a drain electrode; and
wherein the array substrate further comprises a first conductive layer formed in the same layer and disposed in intervals with the gate electrode of the TFT on the insulating layer; wherein the first conductive layer is located below the drain electrode, the dielectric isolation layer has a third contact hole to expose the first conductive layer, the first conductive layer is electrically connected to the drain electrode via the third contact hole;
the array substrate further comprising a second conductive layer formed in the same layer and disposed in intervals with the shading metal layer on the substrate; the second conductive layer is located below the first conductive layer; the buffer layer has a fourth contact hole to expose the second conductive layer, the second conductive layer is electrically connected to the polycrystalline semiconductor layer via the fourth contact hole, by overlapping disposed, the insulation layer sandwiched by the polycrystalline semiconductor layer and the first conductive layer to form a MIS storage capacitor.

2. The array substrate according to claim 1 , wherein a portion of the metal layer is corresponding to locate above the TFT, and another portion of the metal layer is in a stripe type and corresponding to formed above the data line of the array substrate.

3. The array substrate according to claim 1 , wherein the second conductive layer is across the effective display area of the array substrate, and is electrically connected to the common electrode in the peripheral area of the effective display area.

4. A liquid crystal display panel, comprising the array substrate according to claim 1 .

5. A liquid crystal display device comprising a liquid crystal display panel and a light source module to provide the backlight to the liquid crystal display panel, wherein the liquid crystal display panel is according to claim 4 .

6. An array substrate, comprising: a substrate; a TFT, a planarization layer, a common electrode, a passivation layer and a pixel electrode sequentially formed on the substrate characterized in that the array substrate further comprising a touch panel insulation layer and a metal layer sequentially formed between the common electrode and the passivation layer; wherein the metal layer is electrically connected to the pixel electrode and the drain electrode of the TFT separately; by overlapping disposed, the insulation portion of the touch panel insulation layer and the passivation layer sandwiched by the common electrode and the pixel electrode to form the first storage capacitor; and by overlapping disposed, the insulation portion of the touch panel insulation layer sandwiched by the metal layer and the common electrode to form the second storage capacitor;
wherein the planarization layer and the touch panel insulation layer have a first contact hole to expose the drain electrode of the TFT and the metal layer is electrically connected to the drain electrode via the first contact hole; the passivation layer has a second contact hole to expose the metal layer and the pixel electrode is electrically connected to the metal layer via the second contact hole;
wherein the TFT comprises a gate electrode, a buffer layer, a polycrystalline semiconductor layer, a dielectric isolation layer, and a source-drain electrode layer formed by a source electrode and a drain electrode; and
wherein the array substrate further comprises a first conductive layer formed in the same layer with the source-drain electrode layer of the TFT and disposed in intervals on the dielectric isolation layer, the first conductive layer is located under the drain electrode, the dielectric isolation layer has a third contact hole to expose the first conductive layer, the first conductive layer is electrically connected to the drain electrode via the third contact hole, and
the array substrate further comprising a second conductive layer formed on the same layer with the gate electrode of the TFT and disposed in intervals on the substrate, wherein the second conductive layer is located below the first conductive layer, the insulating layer has a fourth contact hole to expose the second conductive layer, the second conductive layer is electrically connected to the polycrystalline semiconductor layer via the fourth contact hole, by overlapping disposed, the dielectric isolation layer sandwiched by the polycrystalline semiconductor layer and the first conductive layer to form a MIS storage capacitor of the array substrate.

7. The array substrate according to claim 6 , wherein the second conductive layer is across the effective display area of the array substrate, and is electrically connected to the common electrode in the peripheral area of the effective display area.

8. A liquid crystal display panel, comprising the array substrate according to claim 6 .

9. A liquid crystal display device comprising a liquid crystal display panel and a light source module to provide the backlight to the liquid crystal display panel, wherein the liquid crystal display panel is according to claim 8 .

Assignees

• Wuhan China Star Optoelectronics Technology Co Ltd
• Wuhan China Star Optoelectronics Technology Co Ltd

Inventors

• Ma Liang

Classifications

• G02F2201/121

  common or background · CPC title

• G02F2201/123

  pixel · CPC title

• G02F1/13338

  Input devices, e.g. touch panels · CPC title

• G02F2001/133357

  Physics · mapped topic

• G02F1/136227

  Through-hole connection of the pixel electrode to the active element through an insulation layer · CPC title