Array substrate having via-hole conductive layer and display device

Patent metadata

Field	Value
Publication number	US-9673231-B2
Application number	US-201615233255-A
Country	US
Kind code	B2
Filing date	Aug 10, 2016
Priority date	Nov 26, 2014
Publication date	Jun 6, 2017
Grant date	Jun 6, 2017

Abstract

Embodiments of the disclosure provide an array substrate having via-hole conductive layer and display device. The array substrate includes: a thin film transistor; a passivation layer, covering the thin film transistor, the passivation layer having a via hole and the via hole exposing at least a portion of a drain electrode of the thin film transistor; a via-hole conductive layer, covering the portion of the drain electrode exposed at the via hole and connected to the drain electrode, and a reflectivity of the via-hole conductive layer being lower than a reflectivity of the drain electrode; and a pixel electrode, connected with the drain electrode through the via-hole conductive layer.

First claim

The invention claimed is:

1. An array substrate, comprising:
a thin film transistor;
a passivation layer, covering the thin film transistor, the passivation layer having a via hole and the via hole exposing at least a portion of a drain electrode of the thin film transistor;
a via-hole conductive layer, covering the portion of the drain electrode exposed at the via hole and connected to the drain electrode, and a reflectivity of the via-hole conductive layer being lower than a reflectivity of the drain electrode; and
a pixel electrode, connected with the drain electrode through the via-hole conductive layer,
wherein the array substrate further comprises gate lines, data lines and pixel units defined by the gate lines and the data lines intersecting with each other, and
wherein the via-hole conductive layer is provided at the via hole so that no portions of the via-hole conductive layer extend into a display region of each of the pixel units.

2. The array substrate according to claim 1 , wherein a surface of the via-hole conductive layer is hazing.

3. The array substrate according to claim 1 , further comprising a common electrode, wherein the via-hole conductive layer and the common electrode layer are disposed in a same layer, and the via-hole conductive layer and the common electrode are disconnected from each other.

4. The array substrate according to claim 1 , wherein the via-hole conductive layer and the pixel electrode are disposed in a same layer, and the via-hole conductive layer and the pixel electrode are connected with each other.

5. The array substrate according to claim 1 , further comprising a black matrix and a color filter layer, wherein the black matrix corresponds to the thin film transistor, and the color filter layer corresponds to the pixel electrode.

6. The array substrate according to claim 5 , wherein the via-hole conductive layer is not overlapped with the color filter layer in a direction perpendicular to the array substrate.

7. The array substrate according to claim 1 , further comprising an organic insulating layer, wherein the organic insulating layer is provided between a layer where the pixel electrode is provided and a layer where the drain electrode is provided.

8. The array substrate according to claim 1 , further comprising a spacer, wherein the spacer is provided in a topmost layer of the array substrate.

9. A display device, comprising the array substrate according to claim 1 .

Assignees

• Boe Technology Group Co Ltd

Inventors

• Shu Shi
• Zhang Feng
• Gu Yaohui
• He Fang
• Gu Feng

Classifications

• H10W20/081

  by forming openings in the dielectric parts · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• G02F2001/136295

  Physics · mapped topic

• G02F2201/121

  common or background · CPC title

• G02F1/13394

  spacers regularly patterned on the cell subtrate, e.g. walls, pillars (G02F1/133377 takes precedence) · CPC title