Three-dimensional memory device with through-stack contact via structures and method of making thereof

Patent metadata

Field	Value
Publication number	US-10283566-B2
Application number	US-201715610918-A
Country	US
Kind code	B2
Filing date	Jun 1, 2017
Priority date	Jun 1, 2017
Publication date	May 7, 2019
Grant date	May 7, 2019

Abstract

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, an array of memory structures, conductive structures located between a substrate and the alternating stack, conductive via structures, including an upper portion that overlies and contacts a top surface of a respective one of the electrically conductive layers, and a lower portion that underlies and is adjoined to the upper portion, contacts a top surface of a respective one of the conductive structures, and is electrically insulated from the rest of the electrically conductive layers. Inner, outer and intermediate dielectric spacers laterally surround a respective one of the conductive via structures.

First claim

What is claimed is:

1. A three-dimensional memory device comprising:
an alternating stack of insulating layers and electrically conductive layers located over a substrate;
an array of memory structures vertically extending through the alternating stack, wherein each of the memory structures includes memory elements located at levels of the electrically conductive layers;
conductive structures located between the substrate and the alternating stack;
conductive via structures, wherein each conductive via structure comprises:
an upper portion that overlies and contacts a top surface of a respective one of the electrically conductive layers; and
a lower portion that underlies and is adjoined to the upper portion, contacts a top surface of a respective one of the conductive structures, and is electrically insulated from a respective subset of the electrically conductive layers that is located between the respective one of the electrically conductive layers and the conductive structures; and

inner, outer and intermediate dielectric spacers which laterally surround a respective one of the conductive via structures;
wherein:
each conductive via structure physically contacts the top surface of the respective one of the electrically conductive layers within a respective area in which none of the electrically conductive layers overlies the respective one of the electrically conductive layers; and
each of the conductive via structures comprises:
a metallic liner comprising a conductive metal nitride and extending through an upper portion and a lower portion of a respective one of the conductive via structures; and
a conductive fill material portion comprising an elemental metal or an intermetallic alloy, embedded within the metallic liner, and extending through the upper portion and the lower portion of the respective one of the conductive via structures.

2. The three-dimensional memory device of claim 1 , wherein:
each of the outer dielectric spacers includes a vertical portion that laterally surrounds a respective one of upper portions of the conductive via structures and an annular base portion contacting a top surface of a respective one of the electrically conductive layers and having a greater lateral extent than the vertical portion; and
each of the inner dielectric spacers contacts a peripheral portion of a respective one of the annular base portions of the outer dielectric spacers and laterally surrounds the respective one of the upper portions of the conductive via structures.

3. The three-dimensional memory device of claim 2 , wherein:
the intermediate dielectric spacers contact an inner sidewall of a respective one of the outer dielectric spacers and an outer sidewall of the respective one of the inner dielectric spacers;
the insulating layers comprise a first silicon oxide material;
the intermediate dielectric spacers comprise a second silicon oxide material;
an etch rate of the second silicon oxide material in dilute hydrofluoric acid including 1 weight percent of hydrofluoric acid in distilled water is at least twice an etch rate of the first silicon oxide material in the dilute hydrofluoric acid;
each of the intermediate dielectric spacers contacts a top surface of respective one of the annular base portions of the outer dielectric spacers; and
each of the inner dielectric spacers contacts a sidewall of a respective one of the upper portions of the conductive via structures.

4. The three-dimensional memory device of claim 2 , further comprising lower dielectric spacers comprising a same material as the inner dielectric spacers, wherein each of the lower dielectric spacers laterally surrounds a respective one of the lower portions of the contact via structures and contacts a bottom surface of the respective one of the upper portions of the conductive via structures.

5. The three-dimensional memory device of claim 1 , wherein:
each of the inner dielectric spacers includes a vertical portion that laterally surrounds a respective one of upper portions of the conductive via structures and an annular base portion contacting a top surface of a respective one of the electrically conductive layers and having a greater lateral extent than the vertical portion; and
each of the outer dielectric spacers overlies a peripheral portion of a respective one of the annular base portions of the inner dielectric spacers and laterally surrounds the respective one of the upper portions of the conductive via structures.

6. The three-dimensional memory device of claim 5 , wherein an outer bottom periphery of each outer dielectric spacer coincides within an upper periphery of an underlying one of the annular base portions of the inner dielectric spacers.

7. The three-dimensional memory device of claim 5 , wherein:
the intermediate dielectric spacers contact an inner sidewall of a respective one of the outer dielectric spacers;
the insulating layers comprise a first silicon oxide material;
the intermediate dielectric spacers comprise a second silicon oxide material; and
an etch rate of the second silicon oxide material in dilute hydrofluoric acid including 1 weight percent of hydrofluoric acid in distilled water is at least twice an etch rate of the first silicon oxide material in the dilute hydrofluoric acid.

8. The three-dimensional memory device of claim 7 , wherein:
the inner dielectric spacers contact an inner sidewall of a respective one of the intermediate dielectric spacers;
each of the outer and intermediate dielectric spacers contacts a top surface of respective one of the annular base portions of the inner dielectric spacers; and
each of the inner dielectric spacers contacts a sidewall of a respective one of the upper portions of the conductive via structures.

9. The three-dimensional memory device of claim 7 , further comprising lower dielectric spacers comprising a same material as the inner dielectric spacers, wherein each of the lower dielectric spacers laterally surrounds a respective one of the lower portions of the contact via structures and contacts a bottom surface of the respective one of the upper portions of the conductive via structures.

10. The three-dimensional memory device of claim 7 , wherein top surfaces of the conductive via structures, the outer dielectric spacers, the intermediate dielectric spacers, and the inner dielectric spacers are located within a same horizontal plane.

11. The three-dimensional memory device of claim 1 , wherein the three-dimensional memory device comprises a resistive random access memory device including vertical bit lines and resistive memory elements located adjacent to each of the vertical bit lines and at each level of the electrically conductive layers within the alternating stack.

12. The three-dimensional memory device of claim 1 , wherein the three-dimensional memory device comprises a monolithic three-dimensional NAND memory device including memory stack structures, wherein each of the memory stack structures comprises a vertical semiconductor channel and charge storage regions located adjacent to the vertical semiconductor channel at levels of the electrically conductive layers within the alternating stack.

13. The three-dimensional memory device of claim 1 , wherein:
the conductive via structures comprise word line contact via structures;
the electrically conductive layers comprise word lines of the three dimensional memory device; and
the conductive via structures electrically connect each word line to a respective peripheral device of a driver circuit located below the alternating stack.

Assignees

• Sandisk Technologies Llc

Inventors

• Sel Jongsun
• Pham Tuan
• Mushiga Mitsuteru
• Ikeda Yoshihiro
• KANG Daewung
• Nishida Akio

Classifications

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/083 Primary

  the openings being via holes penetrating underlying conductors · CPC title

• H10W20/076

  in via holes or trenches · CPC title

• H10W20/42 Primary

  Vias, e.g. via plugs · CPC title

• H01L27/2481 Primary

  Electricity · mapped topic