Fully isolated selector for memory device

Patent metadata

Field	Value
Publication number	US-9437658-B2
Application number	US-201414451664-A
Country	US
Kind code	B2
Filing date	Aug 5, 2014
Priority date	Aug 5, 2014
Publication date	Sep 6, 2016
Grant date	Sep 6, 2016

Abstract

A monolithic, three-dimensional memory device includes a substrate and a plurality of electrically conductive word lines over a major surface of the substrate. An electrically conductive bit line extends in a direction substantially perpendicular to the major surface of the substrate and adjacent to each of the plurality of word lines, and a non-volatile memory element material is located between the bit line and each of the plurality of word lines. A plurality of middle electrodes comprising an electrically conductive material are located between the bit line and each of the plurality of word lines, wherein the plurality of middle electrodes are discrete electrodes which are isolated from one another in at least the second direction.

First claim

What is claimed is:

1. A monolithic, three-dimensional memory device, comprising:
a substrate having a major surface;
a plurality of electrically conductive word lines over the major surface of the substrate, wherein each word line is elongated in a first direction that is substantially parallel to the major surface of the substrate and the plurality of word lines are spaced apart from one another in a second direction that is substantially perpendicular to the major surface of the substrate, and an electrically insulating material is located between each of the spaced apart word lines;
an electrically conductive bit line extending in a direction substantially perpendicular to the major surface of the substrate and adjacent to each of the plurality of word lines;
a non-volatile memory element material located between the bit line and each of the plurality of word lines; and
a plurality of middle electrodes comprising an electrically conductive material located between the bit line and each of the plurality of word lines, wherein the plurality of middle electrodes are discrete electrodes which are isolated from one another in at least the second direction.

2. The device of claim 1 , further comprising:
a non-linear element located between the bit line and each of the plurality of word lines.

3. The device of claim 2 , wherein each of the middle electrodes is adjacent to the non-volatile memory element material and electrically connects the non-volatile memory element material in series with the non-linear element.

4. The device of claim 2 , wherein the non-linear element comprises a Schottky junction.

5. The device of claim 2 , wherein the non-linear element comprises a tunnel junction.

6. The device of claim 2 , wherein the non-linear element comprises a metal-insulator-metal (MIM) junction.

7. The device of claim 2 , wherein the non-linear element is formed by providing a layer of insulating material over at least one side surface of the bit line.

8. The device of claim 1 , wherein the plurality of middle electrodes are located between the non-volatile memory element material and the bit line.

9. The device of claim 1 , wherein the plurality of middle electrodes are located between the non-volatile memory element and the word lines.

10. The device of claim 1 , wherein the bit line comprises a generally pillar-shaped structure having at least one side surface, and the non-volatile memory element material comprises a continuous layer that extends over a side surface of the bit line and adjacent to each of the plurality of word lines.

11. The device of claim 10 , wherein:
the layer of non-volatile memory element material comprises a plurality of clam shape portions adjacent to each of the plurality of word lines;
each of the clam shape portions surrounds a respective one of the plurality of middle electrodes on three sides;
the bit line comprises the generally pillar-shaped structure having a substantially rectangular cross section;
the non-linear element is located adjacent to all four sidewalls of the substantially-pillar shaped bit line; and
the a plurality of middle electrodes are located adjacent to two of four sidewalls of the substantially-pillar shaped bit lines.

12. The device of claim 1 , wherein the monolithic, three-dimensional memory device comprises a ReRAM memory device.

13. The device of claim 1 , wherein the electrically conductive bit line comprises a local bit line that is electrically connected to a global bit line via a select transistor.

14. The device of claim 1 , wherein the non-volatile memory element material comprises a material in which discrete regions of the material located between the bit line and each of the plurality of word lines are controllably alternated between a more conductive state and a less conductive state by appropriate voltages applied to the bit line and the respective word line.

15. The device of claim 14 , wherein the non-volatile memory element material comprises a metal oxide.

Assignees

• Sandisk 3D Llc
• Sandisk Technologies Llc

Inventors

• Sakotsubo Yukihiro

Classifications

• H01L27/2409

  Electricity · mapped topic

• H01L27/249

  Electricity · mapped topic

• H01L45/1253

  Electricity · mapped topic

• H01L27/2418

  Electricity · mapped topic

• H01L45/08

  Electricity · mapped topic