Multilevel contact to a 3D memory array and method of making thereof

Patent metadata

Field	Value
Publication number	US-9449924-B2
Application number	US-201314136103-A
Country	US
Kind code	B2
Filing date	Dec 20, 2013
Priority date	Dec 20, 2013
Publication date	Sep 20, 2016
Grant date	Sep 20, 2016

Abstract

A multi-level device includes at least one device region and at least one contact region. The contact region has a stack of alternating plurality of electrically conductive layers and plurality of electrically insulating layers located over a substrate. The plurality of electrically conductive layers form a stepped pattern in the contact region, where each respective electrically insulating layer includes a sidewall and a respective underlying electrically conductive layer in the stack extends laterally beyond the sidewall.

First claim

What is claimed is:

1. A multilevel device, comprising:
at least one device region and at least one contact region having a stack of alternating plurality of electrically conductive layers and plurality of electrically insulating layers located over a substrate, wherein the plurality of electrically conductive layers form a stepped pattern in the contact region, wherein each electrically insulating layer comprises a sidewall and a respective underlying electrically conductive layer in the stack extends laterally beyond the sidewall to a respective sidewall surface; and
a plurality of electrically conductive sidewall spacers located adjacent to a respective sidewall of the electrically insulating layers, wherein each of the electrically conductive sidewall spacers is in electrical contact with a respective underlying electrically conductive layer and is substantially electrically isolated from the other electrically conductive layers in the plurality of electrically conductive layers in the stack, and wherein each of the electrically conductive sidewall spacers includes a sidewall surface that is within a same vertical plane as a sidewall surface of the respective underlying electrically conductive layer.

2. The device of claim 1 , wherein each of the plurality of sidewall spacers extends vertically past a set of electrically conductive layers in the stack which overlies the respective electrically insulating layer.

3. The device of claim 2 , wherein each of the plurality of sidewall spacers contacts a contact portion of a respective electrically conductive layer corresponding to the stepped pattern, wherein the contact portion extends laterally past any overlying electrically conductive layers in the stack.

4. The device of claim 3 , further comprising an electrically insulating fill material that substantially fills a lateral space between each pair of laterally adjacent sidewall spacers.

5. The device of claim 4 , wherein the electrically insulating fill material in the contact region comprises a layer having a flat top exposing tops of the plurality of sidewall spacers.

6. The device of claim 1 , further comprising:
an overlying insulating layer located over the contact region;
an electrically conductive via connection extending vertically through the overlying insulating layer to make electrical contact with at least one of the plurality of sidewall spacers;
wherein each of the plurality of sidewall spacers extends laterally past the via connection at a location where the via connection contacts the sidewall spacer.

7. The device of claim 6 , wherein each of the plurality of sidewall spacers has a lateral cross sectional area that is greater than a lateral cross sectional area of the via connection at the location where the via connection contacts the sidewall spacer.

8. The device of claim 1 , wherein at least one of the plurality of sidewall spacers has a substantially L-shaped vertical cross section comprising a upper arm extending substantially vertically from a side of a substantially horizontal lower base arm that has a greater width than the upper arm.

9. The device of claim 8 , further comprising a filler material that fills a space defined by the L-shaped vertical cross section between and adjacent to the upper arm and the lower base arm.

10. The device of claim 8 , wherein a sidewall surface of each substantially horizontal lower base arm is within a same vertical plane as a sidewall surface of a respective underlying electrically conductive layer.

11. The device of claim 10 , wherein the upper arm of each electrically conductive sidewall spacer is laterally offset from the sidewall surface of the electrically conductive sidewall spacer.

12. The device of claim 1 , wherein:
the device comprises a vertical NAND device; and
at least one of the electrically conductive layers in the stack comprises or is electrically connected to a word line of the NAND device.

13. The device of claim 12 , wherein:
the device region comprises:
a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a major surface of the substrate; and
a plurality of charge storage regions, each charge storage region located adjacent to a respective one of the plurality of semiconductor channels; and
a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate, wherein the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level;
a first one of the plurality of electrically conductive layers in the stack is in electrical contact with the first control gate electrode and extends from the device region to the contact region; and
a second one of the plurality of electrically conductive layers in the stack is in electrical contact the second control gate electrode and extends from the device region to the contact region.

14. The device of claim 1 , wherein:
the device comprises a three dimensional ReRAM device; and
at least one of the electrically conductive layers in the stack comprises or is electrically connected to an electrode of the ReRAM device.

15. The device of claim 1 , wherein all top surfaces of the plurality of electrically conductive sidewall spacers are within a same horizontal plane.

16. The device of claim 15 , further comprising an insulating layer overlying the alternating stack, wherein a top surface of the insulating layer is within the same horizontal plane including all top surfaces of the plurality of electrically conductive sidewall spacers.

17. The device of claim 15 , wherein the same horizontal plane including all top surfaces of the plurality of electrically conductive sidewall spacers is located above a horizontal plane including a top surface of a topmost electrically conductive layer among the plurality of electrically conductive layers.

18. The device of claim 15 , wherein at least one sidewall surface of the plurality of electrically conductive sidewall spacers adjoins the same horizontal plane at a non-orthogonal angle.

19. The device of claim 1 , wherein at least one of the plurality of electrically conductive sidewall spacers has a non-vertical sidewall having a lateral distance from a vertical line passing through the sidewall surface of the respective underlying electrically conductive layer that increases with a vertical distance with the respective underlying electrically conductive layer.

20. A monolithic, three dimensional array of memory devices located over a silicon substrate, comprising:
an array of vertically oriented NAND strings in which at least one memory cell in a first device level of the array is located over another memory cell in a second device level;
an integrated circuit comprising a driver circuit for the array of memory devices located on the silicon substrate;
at least one device region and at least one contact region having a stack of alternating plurality of electrically conductive layers and plurality of electrically insulating layers located over a substrate, wherein the plurality of electrically conductive layers form a stepped pattern in the contact region, wherein each electrically insulating layer comprises a sidewall and a respective underlying electrically conductive layer in the stack extends laterally beyond the sidewall to a respective sidewall surface;

Assignees

• Sandisk 3D Llc
• Sandisk Technologies Llc

Inventors

• Takaki Seje

Classifications

• H10W20/0698

  Local interconnections · CPC title

• H10W20/20 Primary

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H01L27/2481

  Electricity · mapped topic

• H01L27/1157

  Electricity · mapped topic

• H01L27/11578

  Electricity · mapped topic