Power grid conductor placement within an integrated circuit

Patent metadata

Field	Value
Publication number	US-9653413-B2
Application number	US-201414307574-A
Country	US
Kind code	B2
Filing date	Jun 18, 2014
Priority date	Jun 18, 2014
Publication date	May 16, 2017
Grant date	May 16, 2017

Abstract

An integrated circuit 2 is formed with standard-cell power conductors 14 which are overlaid by power grid conductors 20 . The power grid conductors are offset in a direction transverse to the longitudinal axis of the power grid conductors relative to their underlying standard-cell power conductor. This has the effect of increasing the conductor spacing possible to one side of the power grid conductor. Accordingly, a wider than minimum width power grid conductor may be provided which blocks only one of its adjacent track positions from being used by a routing conductor 22.

First claim

We claim:

1. An integrated circuit comprising:
a plurality of standard cells having a plurality of standard-cell conductors in a standard-cell conductor layer, said plurality of standard-cell conductors disposed substantially parallel to each other; and
a plurality of further conductors in a further layer separate from said standard-cell conductor layer, said plurality of further conductors disposed substantially parallel with said plurality of standard-cell power conductors, wherein
at least one of said further conductors is disposed at an offset position relative to a sequence of conductors starting at a boundary of a standard cell and with longitudinal axis spaced by a uniform pitch from each other.

2. An integrated circuit as claims in claim 1 , wherein said plurality of standard cell conductors include standard cell signal routing conductors within said plurality of standard cells and said plurality of further conductors include further layer signal routing conductors within said further layer.

3. An integrated circuit comprising:
a plurality of standard cells having a plurality of standard-cell conductors in a standard-cell conductor layer, said plurality of standard-cell conductors disposed substantially parallel to each other; and
a plurality of further conductors in a further layer separate from said standard-cell conductor layer, said plurality of further conductors disposed substantially parallel with said plurality of standard-cell power conductors, wherein
at least one of said further conductors is disposed at an offset position relative to a sequence of conductors starting at a boundary of a standard cell and with longitudinal axis spaced by a uniform pitch from each other, wherein:
said plurality of standard cell conductors include a plurality of standard cell power conductors and said plurality of standard cells are connected to draw power from said plurality of standard-cell power conductors; and
said plurality of further conductors include a plurality power grid conductors in a further layer separate from said standard-cell conductor layer, said plurality of power grid conductor disposed substantially parallel with and overlapping corresponding ones of said plurality of standard-cell power conductors, wherein
at least one of said power grid conductors is disposed overlapping a corresponding one of said plurality of standard-cell power conductors and has a grid-conductor median longitudinal axis offset by an offset distance in a direction within said further layer, and transverse to said grid-conductor longitudinal median axis, from a perpendicular projection into said further layer of a standard-cell power-conductor median longitudinal axis of said corresponding one of said plurality of standard-cell power conductors.

4. An integrated circuit as claimed in claim 3 , comprising a plurality of routing conductors in said further layer, said plurality of routing conductors disposed substantially parallel with said plurality of power grid conductors.

5. An integrated circuit as claimed claim 4 , wherein said plurality of power grid conductors and said plurality of routing conductors and are disposed at distances from each other meeting a minimum conductor spacing requirement.

6. An integrated circuit as claimed in claim 4 , wherein at least some of said plurality of routing conductors have a routing-conductor width and are disposed at relative to one another such that a distance between adjacent ones of said plurality of routing conductors is substantially equal to a minimum distance that meets said minimum conductor spacing requirement.

7. An integrated circuit as claimed in claim 4 , wherein at least some said plurality of routing conductors are spaced from each other by a substantially constant conductor pitch value.

8. An integrated circuit as claimed in claim 7 , wherein a position for a routing conductor disposed following said substantially constant pitch value that would violate said minimum conductor spacing requirement is left vacant.

9. An integrated circuit as claimed in claim 4 , wherein said at least one of said power grid conductors is neighboured by a first neighbouring routing conductor and a second neighbouring routing conductor and said offset is such that such that said at least one of said power grid conductors is closer to said first neighbouring routing conductor than to said second neighbouring routing conductor.

10. An integrated circuit as claimed in claim 4 , wherein said plurality of power grid conductors have a greater width in said further layer than said plurality of routing conductors.

11. An integrated circuit as claimed in claim 3 , wherein said standard-cell power conductors are connected to said power grid power conductors with power connection vias.

12. An integrated circuit as claimed in claim 3 , wherein said plurality of standard-cell power conductors and said plurality of power grid conductors are disposed along opposite parallel edges of said standard cells.

13. An integrated circuit as claimed in claim 3 , wherein
at least some said plurality of routing conductors are spaced from each other by a substantially constant conductor pitch value P and said plurality of standard cells have a dimension perpendicular to said plurality of routing conductors and parallel to said standard-cell layer that is N*P, where N is a positive integer value greater than 3, and
adjacent power grid conductors within said plurality of power grid conductor are offset.

14. An integrated circuit as claimed in claim 3 , wherein
at least some said plurality of routing conductors are spaced from each other by a substantially constant conductor pitch value P and said plurality of standard cells have a dimension perpendicular to said plurality of routing conductors and parallel to said standard-cell layer that is N*(P/2), where N is a positive integer value greater than 6, and
alternating ones of said plurality of power grid conductor are offset.

15. An integrated circuit as claimed in claim 3 , wherein said standard-cell conductor layer is a metal one layer of said integrated circuit.

16. An integrated circuit as claimed in claim 15 , wherein said further layer is a metal two layer of said integrated circuit.

Assignees

• Advanced Risc Mach Ltd

Inventors

• Frederick Jr Marlin Wayne
• Delk Karen Lee

Classifications

• H10W20/427

  Power or ground buses · CPC title

• H10W42/00 Primary

  Arrangements for protection of devices (arrangements for thermal protection H10W40/00) · CPC title

• G06F30/394

  Routing (G06F30/396 takes precedence) · CPC title

• H01L2924/0002

  Electricity · mapped topic

• G06F17/5077

  Physics · mapped topic