Circuit with combined cells and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-2017345809-A1
Application number	US-201615264168-A
Country	US
Kind code	A1
Filing date	Sep 13, 2016
Priority date	May 31, 2016
Publication date	Nov 30, 2017
Grant date	—

Abstract

In some embodiments, a first cell layout and a second cell layout are provided and combined into a third cell layout. Each of the first cell layout and the second cell layout includes a higher power line, a lower power line, an output pin, at least one up transistor and at least one down transistor formed to electrically couple the output pin to the higher power line and the output pin to the lower power line, respectively. The at least one up transistor and the at least one down transistor of the second cell layout include a gate line. For the combining, the gate line is non-selectively electrically coupled to the output pin of the first cell layout to form a first node. A design layout in which the third cell layout is used at different locations is generated.

First claim

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9 . A method, comprising:
providing a first cell layout and a second cell layout;
the first cell layout comprising:
a first higher power line and a first lower power line;
a first output pin;
at least one first up transistor formed to electrically couple the first output pin to the first higher power line; and
at least one first down transistor formed to electrically couple the first output pin to the first lower power line;

the second cell layout comprising:
a second higher power line and a second lower power line;
a second output pin;
at least one second up transistor formed to electrically couple the second output pin to the second higher power line;
at least one second down transistor formed to electrically couple the second output pin to the second lower power line;
the at least one second up transistor and the at least one second down transistor comprising a first gate line;

combining the first cell layout and the second cell layout into a third cell layout comprising:
non-selectively electrically coupling the first gate line to the first output pin to form a first node; and
generating, by at least one processor, a design layout in which the third cell layout is used at different locations.

10 . The method of claim 9 , wherein the combining further comprises:
combining a first source or drain region of one of the at least one first up transistor and the at least one first down transistor with a second source or drain region of one of the at least one second up transistor and the at least one second down transistor of a same conductivity type as the first source or drain region during;
during the combining, the first higher power line and the second higher power line being combined into a higher power line and the first lower power line and second lower power line being combined into a lower power line; and
forming a second node;
the second node comprising:
a first conductive line overlapped with one of the first source or drain region and the second source or drain region and non-selectively electrically coupled to the one of the first source or drain region and the second source or drain region and to one of the higher power line and lower power line corresponding to the one of the first source or drain region and the second source or drain region; and
a second conductive line in substantially the same direction as the first conductive line and non-selectively electrically coupled to the one of the higher power line and the lower power line.

11 . The method of claim 10 , wherein the combining further comprises:
reordering a plurality of transistors in series in one of the at least one first up transistor, the at least one second up transistor, the at least one first down transistor and the at least one second down transistor corresponding to the one of the first source or drain region and the second source or drain region so as to enable the forming of the second node.

12 . The method of claim 10 , wherein the combining further comprises:
forming a plurality of gate finger lines non-selectively electrically coupled to each other;
one of the plurality of gate finger lines being adjacent to the one of the first source or drain region and the second source or drain region so as to enable forming of the second node.

13 . The method of claim 10 , wherein
the first source or drain region and the second source or drain region are combined through joining; the first source or drain region and the second source or drain region are joined to opposite sides of a joint portion; and the second conductive line resides in the joint portion.

14 . The method of claim 10 , wherein
the first source or drain region and the second source or drain region are combined through joining; the first source or drain region and the second source or drain region are joined to opposite sides of a second gate line; and the second conductive line overlaps with the other of the first source or drain region and the second source or drain region.

15 . The method of claim 10 , wherein
the first second source or drain region and the second source or drain region are combined through sharing with each other; the second conductive line overlaps with the other of the first source or drain region and the second source or drain region and is shared with the first conductive line.

16 . The method of claim 9 , wherein
the generating the design layout comprises:
setting an area of the third cell layout in a cell library to be smaller than a sum of areas of the first cell layout and the second cell layout in the cell library; and
logic synthesizing a netlist of the design layout using the cell library.

17 . The method of claim 9 , further comprising:
placing a first design layout;
the first design layout comprising:
the first cell layout; and
the second cell layout;
the first output pin being to be routed to the first gate line;

the generating the design layout comprises:
swapping the first cell layout and the second cell layout in the first design layout with the third cell layout to generate a second design layout; and
re-placing the second design layout to generate the design layout.

18 . The method of claim 17 , further comprising:
selecting the first cell layout and the second cell layout in the first design layout for the swapping based on a distance between the first output pin of the first cell layout and the first gate line of the second cell layout being within a range of about 1-5 times of a cell height of the first cell layout.

19 . The method of claim 17 , further comprising:
selecting the first cell layout and the second cell layout in the first design layout for the swapping based on the first output pin and the first gate line correspond to end points in a two-pin net in a netlist corresponding to the first design layout.

20 . A method, comprising:
providing a first cell layout and a second cell layout;
the first cell layout comprising:
a first higher power line and a first lower power line;
a first output pin;
at least one first up transistor formed to electrically couple the first output pin to the first higher power line; and
at least one first down transistor formed to electrically couple the first output pin to the first lower power line;

the second cell layout comprising:
a second higher power line and a second lower power line;
a second output pin;
at least one second up transistor formed to electrically couple the second output pin to the second higher power line;
at least one second down transistor formed to electrically couple the second output pin to the second lower power line; and
the at least one second up transistor and the at least one second down transistor comprising a first gate line;

combining the first cell layout and the second cell layout into a third cell layout comprising:
non-selectively electrically coupling the first gate line to the first output pin to form a first node; and
generating, by at least one processor, a design layout in which the third cell layout is used; and manufacturing an integrated circuit chip based on the design layout.

21 . The method of claim 20 , wherein the combining further comprises:
combining a first source or drain region of one of the at least one first up transistor and the at least one first down transisto

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chang Fong-Yuan
• Lu Lee-Chung
• Cheng Yi-Kan
• Chen Sheng-Hsiung
• Huang Po-Hsiang
• Chen Shun Li
• Lee Jeo-Yen
• Chang Jyun-Hao
• Wang Shao-Huan
• Chen Chien-Ying

Classifications

• G06F2119/12

  Timing analysis or timing optimisation · CPC title

• G06F30/392

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F17/505

  Physics · mapped topic

• H01L27/0207 Primary

  Electricity · mapped topic

• H01L23/5286

  Electricity · mapped topic