Coarse grid design methods and structures
US-9336344-B2 · May 10, 2016 · US
Integrated circuit cell library for multiple patterning
US9633987B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9633987-B2 |
| Application number | US-201414195600-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 3, 2014 |
| Priority date | Mar 5, 2007 |
| Publication date | Apr 25, 2017 |
| Grant date | Apr 25, 2017 |
How to read this patent
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
- Title
What the patent document calls the invention.
- Abstract
A short plain-language summary of the technical disclosure.
- Assignees and inventors
Who owns or filed the patent and who is credited as inventor.
- Key dates
Filing, priority, publication, and grant dates set the timeline.
- First independent claim
The legal scope of protection — read this for what is actually claimed.
- CPC / IPC classifications
Technology tags used to group this patent with similar filings.
- Citations and related patents
Prior art links and similar publications in this corpus.
Abstract
Official abstract text for this publication.
A method is disclosed for defining a multiple patterned cell layout for use in an integrated circuit design. A layout is defined for a level of a cell in accordance with a dynamic array architecture so as to include a number of layout features. The number of layout features are linear-shaped and commonly oriented. The layout is split into a number of sub-layouts for the level of the cell. Each of the number of layout features in the layout is allocated to any one of the number of sub-layouts. Also, the layout is split such that each sub-layout is independently fabricatable. The sub-layouts for the level of the cell are stored on a computer readable medium.
First claim
Opening claim text (preview).
What is claimed is: 1. A semiconductor chip, comprising: a gate electrode level including a plurality of linear-shaped conductive structures defined to extend lengthwise in a first direction, the plurality of linear-shaped conductive structures positioned in accordance with a fixed pitch such that a distance as measured in a second direction perpendicular to the first direction between first-direction-oriented-lengthwise-centerlines of any two of the plurality of linear-shaped con…
Assignees
Inventors
Classifications
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Patent family
Related publications grouped by family.
External sources
Next steps
Free tools are coming soon. Tell us what you want to track and we'll notify you.
Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US9633987B2 cover?
- A method is disclosed for defining a multiple patterned cell layout for use in an integrated circuit design. A layout is defined for a level of a cell in accordance with a dynamic array architecture so as to include a number of layout features. The number of layout features are linear-shaped and commonly oriented. The layout is split into a number of sub-layouts for the level of the cell. Each …
- Who is the assignee on this patent?
- Tela Innovations Inc
- What technology area does this patent fall under?
- Primary CPC classification H01L27/0207. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Apr 25 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 6 related publications on this page (citations in our corpus or others sharing the same primary CPC).