Efficient preemption for graphics processors

Patent metadata

Field	Value
Publication number	US-10282227-B2
Application number	US-201414543982-A
Country	US
Kind code	B2
Filing date	Nov 18, 2014
Priority date	Nov 18, 2014
Publication date	May 7, 2019
Grant date	May 7, 2019

Abstract

Systems and methods may provide for inserting one or more preemption instructions while compiling a computer program. The one or more preemption instructions being inserted within a preemption window in the computer program reduces the number of live registers at each preemption instruction position. Further, the preemption instruction instructs which registers are to be saved at a particular program position, typically the registers that are live at that program position. The compiled program may be run in an execution unit. A preemption request may be made to the execution unit and executed at a next available preemption instruction in the program being run in the execution unit.

First claim

We claim:

1. A computing system comprising:
a data interface to accept a preemption request;
a compiler having a preemption instruction creator and inserter to:
create a preemption window as an interval between two preemption instructions; and
create and insert one or more extra preemption instructions, not part of a computer program and including a first field having one or more bits that define a preemption command itself and a second field having one or more bits that each independently specify a corresponding register to be saved at a particular program position, at one or more locations in the computer program based on where a number of live registers to be saved is at a local minimum within the preemption window;

an execution unit coupled to the compiler and the data interface to execute a compiled computer program with the one or more extra preemption instructions, the execution unit including a plurality of registers in a general purpose register or an architecture register; and
memory communicating with the execution unit to store contents of live registers upon execution of the preemption request.

2. A computer system according to claim 1 , the execution unit further comprising a control flow stack.

3. A computer system according to claim 1 , further comprising an application instruction pointer associated with the execution unit.

4. A computer system according to claim 1 , further comprising a timer communicating with the execution unit.

5. A method of processing a preemption request comprising:
creating a preemption window as an interval between two preemption instructions;
creating and inserting one or more extra preemption instructions, not part of a computer program and including a first field having one or more bits that define a preemption command itself and a second field having one or more bits that each independently specify a corresponding register to be saved at a particular program position, while compiling the computer program, at one or more locations in the computer program based on where a number of live registers to be saved is at a local minimum within the preemption window;
running a compiled program with the one or more extra preemption instructions in an execution unit;
making a preemption request to the execution unit; and
executing the preemption request at a next available preemption instruction in the compiled program being run in the execution unit.

6. A method according to claim 5 , further comprising saving register contents of the live registers to be saved in a memory at a location of a preemption instruction.

7. A method according to claim 6 , wherein the live registers are registers contained in the general register files or the architecture register files.

8. A method according to claim 5 , further comprising saving contents of a control flow stack at a location of a preemption instruction.

9. A method according to claim 5 , further comprising saving a position of an application instruction pointer at a position of execution of the preemption request.

10. A method according to claim 5 , wherein the preemption window defines a length of estimated execution time between the two preemption instructions.

11. A method according to claim 5 , further comprising analyzing the computer program to determine the one or more locations to insert the one or more preemption instructions.

12. At least one non-transitory computer readable storage medium comprising a set of instructions which, when executed by a computing system, cause the computing system to:
create a preemption window as an interval between two preemption instructions;
create and insert one or more extra preemption instructions, not part of a computer program and including a first field having one or more bits that define a preemption command itself and a second field having one or more bits that each independently specify a corresponding register to be saved at a particular program position, while compiling the computer program, at one or more locations in the computer program based on where a number of live registers to be saved is at a local minimum within the preemption window;
run a compiled program with the one or more extra preemption instructions in an execution unit; and
execute a preemption request at a next available preemption instruction in the compiled program being run in the execution unit.

13. The at least one computer readable storage medium of claim 12 , wherein the instructions, when executed, cause a computing system to save register contents of the live registers to be saved in a memory at a location of a preemption instruction.

14. The at least one computer readable storage medium of claim 12 , wherein the instructions, when executed, cause a computing system to save contents of a control flow stack at a location of a preemption instruction.

15. The at least one computer readable storage medium of claim 12 , wherein the instructions, when executed, cause a computing system to save a position of an application instruction pointer at a position of execution of the preemption request.

16. The at least one computer readable storage medium of claim 12 , wherein the preemption window defines a length of estimated execution time between the two preemption instructions.

17. The at least one computer readable storage medium of claim 12 , wherein the instructions, when executed, cause a computing system to analyze the computer program to determine the one or more locations to insert the one or more preemption instructions.

18. An apparatus comprising:
a compiler having a preemption instruction creator and inserter to:
create a preemption window as an interval between two preemption instructions; and
create and insert one or more extra preemption instructions, not part of a computer program and including a first field having one or more bits that define a preemption command itself and a second field having one or more bits that each independently specify a corresponding register to be saved at a particular program position, at one or more locations in the computer program based on where a number of live registers to be saved is at a local minimum within the preemption window;

an execution unit coupled to the compiler to execute a compiled computer program with the one or more extra preemption instructions, the execution unit including a plurality of registers in a general purpose register or an architecture register; and
memory communicating with the execution unit to store contents of live registers upon execution of a preemption request.

19. The apparatus of claim 18 , the execution unit further comprising a control flow stack.

20. The apparatus of claim 18 , further comprising an application instruction pointer associated with the execution unit.

21. The apparatus of claim 18 , further comprising a timer to communicate with the execution unit.

22. The apparatus of claim 18 , wherein the preemption window is to be created based on estimated execution time of subsequent instructions relative to a candidate insertion point, execution penalty relative to instruction over-insertion, and system responsiveness relative to program forward progress.

Assignees

• Intel Corp

Inventors

• Lueh Guei-Yuan
• Maiyuran Subramaniam
• Chen Wei-Yu
• Chen Kaiyu

Classifications

• G06F9/462 Primary

  with multiple register sets · CPC title

• G06F9/3851

  from multiple instruction streams, e.g. multistreaming · CPC title

• G06F9/3009

  Thread control instructions · CPC title

• G06F9/30043

  LOAD or STORE instructions; Clear instruction · CPC title

• G06F9/30076

  to perform miscellaneous control operations, e.g. NOP · CPC title