Privilege level aware processor hardware resource management facility

Patent metadata

Field	Value
Publication number	US-9342337-B2
Application number	US-201314057178-A
Country	US
Kind code	B2
Filing date	Oct 18, 2013
Priority date	Oct 3, 2011
Publication date	May 17, 2016
Grant date	May 17, 2016

Abstract

Multiple machine state registers are included in a processor core to permit distinction between use of hardware facilities by applications, supervisory threads and the hypervisor. All facilities are initially disabled by the hypervisor when a partition is initialized. When any access is made to a disabled facility, the hypervisor receives an indication of which facility was accessed and sets a corresponding hardware flag in the hypervisor's machine state register. When an application attempts to access a disabled facility, the supervisor managing the operating system image receives an indication of which facility was accessed and sets a corresponding hardware flag in the supervisor's machine state register. The multiple register implementation permits the supervisor to determine whether particular hardware facilities need to have their state saved when an application context swap occurs and the hypervisor can determine which hardware facilities need to have their state saved when a partition swap occurs.

First claim

What is claimed is:

1. A method of tracking usage of hardware facilities within a processor core of a computer system by processes executing at different privilege levels, the method comprising:
at a first privilege level, first controlling, including setting and clearing, a state of a first hardware flag in a first register of the processor core that indicates whether or not a corresponding particular hardware facility is enabled for access at another privilege level lower than the first privilege level; and
at a second privilege level lower than the first privilege level, second controlling, including setting and clearing, a second hardware flag in a second register of the processor core that indicates whether or not the particular hardware facility is enabled for access at a third privilege level lower than the second privilege level.

2. The method of claim 1 , wherein the first privilege level is a hypervisor privilege level and wherein the second privilege level is a supervisory privilege level.

3. The method of claim 2 , wherein the first controlling comprises:
at the hypervisor privilege level, clearing the first register to indicate that a plurality of hardware facilities are disabled for access at the another privilege level;
at the hypervisor privilege level, receiving a first indication that a given one of the plurality of hardware facilities has been has been accessed at the another privilege level;
at the hypervisor privilege level, determining from the first indication that the given hardware facility is the particular hardware facility; and
at the hypervisor privilege level, setting the first hardware flag to enable the particular hardware facility for access at the another privilege level.

4. The method of claim 3 , wherein the first indication is a hypervisor interrupt, and wherein the particular hardware facility is indicated in conjunction with the hypervisor interrupt by a field within a first status register of the processor core.

5. The method of claim 3 , wherein the second controlling comprises:
at the supervisor privilege level, clearing the second register to indicate that the plurality of hardware facilities are disabled for access at the third privilege level;
at the supervisor privilege level, receiving a second indication that the given hardware facility has been has been accessed at the third privilege level;
at the supervisor privilege level, determining from the second indication that the given hardware facility is the particular hardware facility; and
at the supervisor privilege level, setting the second hardware flag to enable the particular hardware facility for access at the third privilege level.

6. The method of claim 5 , wherein the second indication is a supervisor interrupt, and wherein the particular hardware facility is indicated in conjunction with the supervisor interrupt by a field within a second status register of the processor core.

7. The method of claim 5 , wherein the setting the first hardware flag sets the first hardware flag to indicate that the particular hardware facility has been enabled for use by a partition executing within the computer system, and wherein the method further comprises:
at the hypervisor privilege level and by a hypervisor, initiating a context swap of the partition; and
determining whether or not to store a state of the particular hardware facility for the partition from an indication of whether the hypervisor has set the first hardware flag.

8. The method of claim 7 , wherein the setting the second hardware flag sets the second hardware flag to indicate that the particular hardware facility has been enabled for use by an application executing within the computer system, and wherein the method further comprises:
at the supervisor privilege level and by a supervisor, initiating a context swap of the application; and
determining whether or not to store a state of the particular hardware facility for the application from an indication of whether the supervisor has set the second hardware flag.

9. The method of claim 1 , further comprising:
initializing a partition;
retrieving a stored context for the partition;
determining whether or not the stored context contains a state for the particular hardware facility;
responsive to determining that the stored context contains the state for the particular hardware facility, restoring the state to the particular hardware facility;
responsive to determining that the stored context does not contain the state for the particular hardware facility, examining the first hardware flag to determine whether the particular hardware facility was in use, and responsive to determining that the particular hardware facility was in use, clearing the contents of the particular hardware facility; and
resetting the first hardware flag and the second hardware flag to disable the particular hardware facility.

10. The method of claim 1 , further comprising:
initializing a partition;
resetting the first hardware flag and the second hardware flag to disable the particular hardware facility;
receiving a first access to the particular hardware facility by an application;
responsive to receiving the first access, determining in a supervisory thread, whether or not to grant access to the particular hardware facility by the application;
responsive to determining that the application should have access to the particular hardware facility, setting the second hardware flag; and
responsive to determining that the application should not have access to the particular hardware facility, maintaining the second hardware flag in the reset state.

Assignees

• IBM

Inventors

• Frazier Giles R
• Gschwind Michael K
• Nayar Naresh

Classifications

• G06F9/45558 Primary

  Hypervisor-specific management and integration aspects · CPC title

• G06F9/462

  with multiple register sets · CPC title

• G06F2009/45579

  I/O management, e.g. providing access to device drivers or storage · CPC title

• G06F9/45533 Primary

  Hypervisors; Virtual machine monitors · CPC title

• G06F9/5077

  Logical partitioning of resources; Management or configuration of virtualized resources (specific details on emulation or internal functioning of virtual machines G06F9/455) · CPC title