System for selecting a task to be executed according to an output from a task control circuit

Patent metadata

Field	Value
Publication number	US-9342350-B2
Application number	US-28133306-A
Country	US
Kind code	B2
Filing date	Aug 24, 2006
Priority date	Aug 24, 2006
Publication date	May 17, 2016
Grant date	May 17, 2016

Abstract

The speed of task scheduling by a multitask OS is increased. A task processor includes a CPU, a save circuit, and a task control circuit. The CPU is provided with a processing register and an execution control circuit operative to load data from a memory into a processing register and execute a task in accordance with the data in the processing register. The save circuit is provided with a plurality of save registers respectively associated with a plurality of tasks. In executing a predetermined system call, the execution control circuit notifies the task control circuit as such. The task control circuit switches between tasks for execution upon receipt of the system call signal, by saving, in the save register associated with a task being executed, the data in the processing register, selecting a task to be executed next, and loading data in the save register associated with the selected task into the processing register.

First claim

What is claimed is:

1. A task processor comprising:
a processor;
a plurality of save registers for saving the data in the processor and that are respectively associated with a plurality of tasks and connected to the processor via a plurality of data lines; and
a task control circuit that controls switching of tasks and is connected to the processor and the plurality of save registers via signal lines,
wherein the processor includes:
a processing register that temporarily stores data for execution of a task; and
an execution control circuit that loads an instruction and an operand from a memory into the processing register, and to execute the task according to the instruction and operand in the processing register,

wherein the execution control circuit includes an instruction decoder that determines whether the instruction to be executed is a predetermined system call instruction or not and transmits a predetermined system call signal to the task control circuit when executing the predetermined system call instruction, the predetermined system call signal not including any information regarding which task to be executed next, and
wherein the task control circuit switches between tasks for execution autonomously upon receipt of the system call signal by:
causing the data stored in the processing register to be saved in the save register associated with a task being executed,
selecting a task to be executed next in accordance with a predetermined rule, by not referring to the system call signal but by referring to context information of each task, and
causing data in the save register associated with the selected task to be loaded into the processing register.

2. The task processor of claim 1 , wherein the execution control circuit halts the supply of a clock for advancing the execution of a task when executing the predetermined system call, and resumes the clock after the data has been loaded from the save register associated with the selected task into the processing register.

3. The task processor of claim 2 , the execution control circuit halts the clock while a plurality of instructions are subjected to a pipeline process, the execution control circuit halting the clock on the condition that the execution of another instruction when the predetermined system call is being executed reaches a predetermined phase that can be suspended.

4. The task processor of claim 2 , wherein the task control circuit transmits a halt request signal to the execution control circuit upon receipt of an interrupt request signal from an external device, and the execution control circuit executes an interrupt task associated with the interrupt request signal upon receipt of the interrupt request signal by halting the clock, loading data for execution of the interrupt task into the processing register, and then resuming the supply of the clock.

5. The task processor of claim 2 , wherein the execution control circuit halts the clock while a plurality of instructions are subjected to a pipeline process and saves an interim result of processing the another instruction in the save registers when in the presence of another instruction being executed when the predetermined system call is executed.

6. The task processor of claim 1 , wherein the data in the processing register is continuously output to the plurality of save registers, and the task control circuit feeds a write signal to the save register associated with the task being executed so as to save, the data in the processing register in the associated save register.

7. The task processor of claim 1 , the task processor further comprising a selector circuit that selects a save register as the source of data transmission when data is loaded from one of the save registers into the processing register, and wherein the data in the plurality of save registers is continuously output to the selector circuit, and the task control circuit transmits an output signal designating the save register associated with the task selected for execution to the selector circuit, thereby loading the data in the associated save register into the processing register.

8. The task processor of claim 1 , wherein the processing register and the plurality of save registers are connected via a bus carrying the number of bits capable of transmitting the data in the processing register in parallel.

9. A task processor comprising:
a processor;
a plurality of save registers for saving the data in the processor and that are respectively associated with a plurality of tasks and connected to the processor via a plurality of data lines; and
a task control circuit that controls switching of tasks and is connected to the processor and the plurality of save registers via signal lines,
wherein the processor includes:
a processing register that temporarily stores data for execution of a task; and
an execution control circuit that loads an instruction and an operand from a memory into the processing register and executes the task according to the instruction and operand in the processing register,

wherein the execution control circuit transmits a predetermined system call signal to the task control circuit when executing a predetermined system call instruction, the predetermined system call signal not including any information regarding which task to be executed next, the system call signal does not indicate what the execution control circuit performs in accordance with the system call instruction but indicates that the system call instruction is detected, and
wherein the task control circuit switches between tasks for execution upon receipt of the system autonomously call signal, by:
causing the data stored in the processing register to be saved, in the save register associated with a task being executed,
selecting a task to be executed next in accordance with a predetermined rule, by not referring to the system call signal but referring to context information of each task, and
causing data in the save register associated with the selected task to be loaded into the processing register.

Assignees

• Maruyama Naotaka
• Renesas Electronics Corp

Inventors

• Maruyama Naotaka

Classifications

• G06F9/30101

  Special purpose registers · CPC title

• G06F9/4806 Primary

  Task transfer initiation or dispatching · CPC title

• G06F9/52 Primary

  Program synchronisation; Mutual exclusion, e.g. by means of semaphores · CPC title

• G06F9/30145

  Instruction analysis, e.g. decoding, instruction word fields · CPC title

• G06F9/30043

  LOAD or STORE instructions; Clear instruction · CPC title